2020-10-12 |
Cole Poirier | fix ModuleNotFound/Import errors found when running... |
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2020-10-08 |
Luke Kenneth Casso... | minor icache cleanup |
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2020-10-08 |
Cole Poirier | second attempt at https://bugs.libre-soc.org/show_bug... |
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2020-10-08 |
Cole Poirier | remove singleton dict per https://bugs.libre-soc.org... |
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2020-10-08 |
Cole Poirier | first attempt at 3) of |
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2020-10-08 |
Cole Poirier | modify wb_get per 1) of https://bugs.libre-soc.org... |
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2020-10-07 |
Tobias Platen | connect mmu_done, ldst_error, cache_paradox |
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2020-10-06 |
Tobias Platen | remove redunant signals |
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2020-10-06 |
Luke Kenneth Casso... | update comments on pimem.py |
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2020-10-06 |
Tobias Platen | test_mmu_dcache_pi.py |
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2020-10-06 |
Luke Kenneth Casso... | passing LDSTException over to Trap Pipeline |
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2020-10-06 |
Luke Kenneth Casso... | make LDSTException fields added from list of fieldnames |
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2020-10-06 |
Luke Kenneth Casso... | move LDSTException to mem_types |
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2020-10-06 |
Luke Kenneth Casso... | add LDSTException to PortInterface |
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2020-10-05 |
Luke Kenneth Casso... | add debug / investigation print statements |
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2020-10-05 |
Cole Poirier | icache.py fix ispow2() util fn per https://bugs.libre... |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | return test rather than "if test return True else False" |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Cole Poirier | icache.py add python asserts that were a TODO commented... |
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2020-10-05 |
Cole Poirier | icache.py fix formatting, mostly due to reduced indenta... |
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2020-10-05 |
Cole Poirier | icache.py remove comment that contained the entirety... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss WAIT_ACK FSM state into... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss CLR_TAG FSM state into metho... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss IDLE FSM state into method... |
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2020-10-02 |
Cole Poirier | icache.py add req_hit_way as arg to icache_comb, actual... |
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2020-10-01 |
Cole Poirier | icache.py add missing comb signal assignments per https... |
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2020-10-01 |
Luke Kenneth Casso... | arg CacheRam read output needs delay by 1 cycle |
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2020-10-01 |
Luke Kenneth Casso... | do not pass cache row array around, just the current row |
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2020-10-01 |
Luke Kenneth Casso... | revert bug in icache wishbone ack |
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2020-10-01 |
Cesar Strauss | Add GTKWave document to test_compunit_fsm |
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2020-09-30 |
Luke Kenneth Casso... | clean up row store and wb adr in icache |
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2020-09-30 |
Luke Kenneth Casso... | hmm only set wishbone address if ack is actually received |
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2020-09-30 |
Luke Kenneth Casso... | add more debug prints in icache |
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2020-09-30 |
Luke Kenneth Casso... | remove more reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | remove reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | comb on wr_index not sync |
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2020-09-30 |
Luke Kenneth Casso... | start removing reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | use same constant name (confusing otherwise) |
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2020-09-30 |
Luke Kenneth Casso... | need asserts |
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2020-09-30 |
Luke Kenneth Casso... | halve the number of icache lines for now |
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2020-09-30 |
Luke Kenneth Casso... | use Repl rather than for-loop to copy bit |
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2020-09-30 |
Luke Kenneth Casso... | move loop invariant test out of loop |
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2020-09-30 |
Luke Kenneth Casso... | reduce size of ilang file by a factor of FIVE |
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2020-09-30 |
Luke Kenneth Casso... | store tag in temp signal |
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2020-09-30 |
Luke Kenneth Casso... | reduce gate usage by getting cache row only not entire... |
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2020-09-30 |
Luke Kenneth Casso... | fix read_tag to use word_select correctly |
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2020-09-30 |
Luke Kenneth Casso... | forgot to add PLRUs as submodules |
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2020-09-29 |
Cole Poirier | icache.py fix combinatorial loop with by testing temp... |
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2020-09-29 |
Cole Poirier | icache.py fix is_last_row_addr, get_next_row_addr |
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2020-09-29 |
Cole Poirier | icache.py trying to sort out test failure, added r... |
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2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
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2020-09-29 |
Cole Poirier | icache.py fix rarange |
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2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
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2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
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2020-09-27 |
Cole Poirier | icache.py fix translation mistake |
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2020-09-27 |
Cesar Strauss | Convert yet another few tests to be able to use latest... |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-09-25 |
Cole Poirier | icache.py fix several subtle bugs that were lines that... |
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2020-09-25 |
Cole Poirier | wb_types.py add reset value of 0b11111111 for WBSelType... |
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2020-09-24 |
Cole Poirier | icache.py add some missing lines from icache.vhdl,... |
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2020-09-24 |
Cole Poirier | mem_types.py wb_types.py add name constructor to all... |
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2020-09-24 |
Cole Poirier | icache.py fixed all errors that raised python exception... |
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2020-09-24 |
Cesar Strauss | Fix whitespace, remove unused imports |
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2020-09-24 |
Luke Kenneth Casso... | brackets round imports looks cleaner? |
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2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
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2020-09-22 |
Cesar Strauss | Port soc.experiment.alu_fsm to the new way of invoking... |
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2020-09-20 |
Cesar Strauss | Add induction proof for the FSM Shifter |
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2020-09-20 |
Cesar Strauss | Add bounded proof to FSM Shifter |
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2020-09-20 |
Cesar Strauss | Let the formal engine create some test cases for the... |
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2020-09-20 |
Luke Kenneth Casso... | resolve issues in async sim: must not drive async clock... |
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2020-09-20 |
Luke Kenneth Casso... | still experimenting with async FF sync |
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2020-09-20 |
Luke Kenneth Casso... | continuing async clock experimenting |
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2020-09-20 |
Luke Kenneth Casso... | add an async clock synchronizer experiment |
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2020-09-20 |
Luke Kenneth Casso... | first version code-morph on dmi2jtag |
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2020-09-19 |
Cesar Strauss | Remove demonstration code |
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2020-09-16 |
Cole Poirier | complete first translation pass of dmi_dtm_xilinx.vhdl... |
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2020-09-16 |
Cole Poirier | initial commit of JTAGToDMI debug interface translated... |
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2020-09-15 |
Luke Kenneth Casso... | comment mmu test |
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2020-09-15 |
Luke Kenneth Casso... | add set MTSPR prtbl to mmu unit test |
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2020-09-15 |
Luke Kenneth Casso... | add extra "modes" to PortInterface |
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2020-09-15 |
Luke Kenneth Casso... | syntax error correction |
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2020-09-15 |
Luke Kenneth Casso... | add inline comments into icache.py |
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2020-09-14 |
Cole Poirier | icache.py add missing funciton bodies, add missing... |
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2020-09-14 |
Luke Kenneth Casso... | increase TLB_NUM_WAYS to 4 |
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2020-09-14 |
Luke Kenneth Casso... | vhdl conversion not really working for plru |
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2020-09-14 |
Luke Kenneth Casso... | add array signal names |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | reorg mmu lookup test so it is called twice |
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2020-09-14 |
Luke Kenneth Casso... | TLB PLRUs are of TLB_WAY_BITS width |
tree | commitdiff |
2020-09-14 |
Luke Kenneth Casso... | fix mmu perms/lookup in dcache |
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2020-09-14 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2020-09-14 |
Luke Kenneth Casso... | remove duplicated signal |
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2020-09-14 |
Luke Kenneth Casso... | comments on icache |
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2020-09-14 |
Luke Kenneth Casso... | get rid of rst |
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2020-09-14 |
Luke Kenneth Casso... | use word_select |
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2020-09-14 |
Luke Kenneth Casso... | add mmu-dcache test |
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