2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
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2020-09-29 |
Cole Poirier | icache.py fix rarange |
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2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
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2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
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2020-09-27 |
Cole Poirier | icache.py fix translation mistake |
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2020-09-27 |
Cesar Strauss | Convert yet another few tests to be able to use latest... |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-09-25 |
Cole Poirier | icache.py fix several subtle bugs that were lines that... |
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2020-09-25 |
Cole Poirier | wb_types.py add reset value of 0b11111111 for WBSelType... |
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2020-09-24 |
Cole Poirier | icache.py add some missing lines from icache.vhdl,... |
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2020-09-24 |
Cole Poirier | mem_types.py wb_types.py add name constructor to all... |
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2020-09-24 |
Cole Poirier | icache.py fixed all errors that raised python exception... |
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2020-09-24 |
Cesar Strauss | Fix whitespace, remove unused imports |
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2020-09-24 |
Luke Kenneth Casso... | brackets round imports looks cleaner? |
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2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
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2020-09-22 |
Cesar Strauss | Port soc.experiment.alu_fsm to the new way of invoking... |
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2020-09-20 |
Cesar Strauss | Add induction proof for the FSM Shifter |
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2020-09-20 |
Cesar Strauss | Add bounded proof to FSM Shifter |
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2020-09-20 |
Cesar Strauss | Let the formal engine create some test cases for the... |
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2020-09-20 |
Luke Kenneth Casso... | resolve issues in async sim: must not drive async clock... |
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2020-09-20 |
Luke Kenneth Casso... | still experimenting with async FF sync |
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2020-09-20 |
Luke Kenneth Casso... | continuing async clock experimenting |
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2020-09-20 |
Luke Kenneth Casso... | add an async clock synchronizer experiment |
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2020-09-20 |
Luke Kenneth Casso... | first version code-morph on dmi2jtag |
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2020-09-19 |
Cesar Strauss | Remove demonstration code |
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2020-09-16 |
Cole Poirier | complete first translation pass of dmi_dtm_xilinx.vhdl... |
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2020-09-16 |
Cole Poirier | initial commit of JTAGToDMI debug interface translated... |
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2020-09-15 |
Luke Kenneth Casso... | comment mmu test |
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2020-09-15 |
Luke Kenneth Casso... | add set MTSPR prtbl to mmu unit test |
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2020-09-15 |
Luke Kenneth Casso... | add extra "modes" to PortInterface |
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2020-09-15 |
Luke Kenneth Casso... | syntax error correction |
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2020-09-15 |
Luke Kenneth Casso... | add inline comments into icache.py |
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2020-09-14 |
Cole Poirier | icache.py add missing funciton bodies, add missing... |
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2020-09-14 |
Luke Kenneth Casso... | increase TLB_NUM_WAYS to 4 |
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2020-09-14 |
Luke Kenneth Casso... | vhdl conversion not really working for plru |
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2020-09-14 |
Luke Kenneth Casso... | add array signal names |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | reorg mmu lookup test so it is called twice |
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2020-09-14 |
Luke Kenneth Casso... | TLB PLRUs are of TLB_WAY_BITS width |
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2020-09-14 |
Luke Kenneth Casso... | fix mmu perms/lookup in dcache |
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2020-09-14 |
Luke Kenneth Casso... | whitespace |
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2020-09-14 |
Luke Kenneth Casso... | remove duplicated signal |
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2020-09-14 |
Luke Kenneth Casso... | comments on icache |
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2020-09-14 |
Luke Kenneth Casso... | get rid of rst |
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2020-09-14 |
Luke Kenneth Casso... | use word_select |
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2020-09-14 |
Luke Kenneth Casso... | add mmu-dcache test |
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2020-09-14 |
Cole Poirier | icache.py connect up all the sub-functions, fix typos... |
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2020-09-14 |
Cole Poirier | icache.py add parameters to 'process' functions, fix... |
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2020-09-13 |
Cole Poirier | icache.py move get/read/write functions out of ICache... |
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2020-09-13 |
Cole Poirier | icache.py copy simulation code from dcache.py, fix... |
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2020-09-13 |
Cole Poirier | icache.py fix syntax, move all constants and Array... |
tree | commitdiff |
2020-09-13 |
Cole Poirier | icache.py fix syntax errors that occured when running... |
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2020-09-13 |
Luke Kenneth Casso... | dcache truncate wishbone address, store real_addr in... |
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2020-09-13 |
Luke Kenneth Casso... | last mmu get seems ok |
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2020-09-13 |
Luke Kenneth Casso... | whoops recursion error v.shift calculated from v.shift |
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2020-09-13 |
Luke Kenneth Casso... | more experimenting with mmu READ_WAIT state |
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2020-09-13 |
Luke Kenneth Casso... | radix tree wait error, investigating |
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2020-09-13 |
Luke Kenneth Casso... | mmu test starting to make sense |
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2020-09-13 |
Luke Kenneth Casso... | floundering around with MMU unit test, no idea what... |
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2020-09-13 |
Luke Kenneth Casso... | mmu code-morph |
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2020-09-13 |
Luke Kenneth Casso... | code-morph, add masked function |
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2020-09-13 |
Luke Kenneth Casso... | move code to mmu_0 |
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2020-09-13 |
Luke Kenneth Casso... | add example radix walk from power-gem5 |
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2020-09-13 |
Luke Kenneth Casso... | MMU test |
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2020-09-13 |
Luke Kenneth Casso... | sort out ariane PLRU, rename/clarify |
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2020-09-13 |
Luke Kenneth Casso... | minor error in plru |
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2020-09-13 |
Luke Kenneth Casso... | rename cache_valid_bits to cache_validsg |
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2020-09-13 |
Luke Kenneth Casso... | cache_valid_idx too large in dcache |
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2020-09-13 |
Luke Kenneth Casso... | whoops, cache valid array too small in dcache |
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2020-09-12 |
Luke Kenneth Casso... | more dcache debugging |
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2020-09-12 |
Luke Kenneth Casso... | missing reservation address comparison |
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2020-09-12 |
Luke Kenneth Casso... | dcache tidyup |
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2020-09-12 |
Luke Kenneth Casso... | more dcache debugging |
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2020-09-12 |
Luke Kenneth Casso... | add random dcache mem test |
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2020-09-12 |
Luke Kenneth Casso... | cache valid corrupted: fixed |
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2020-09-12 |
Luke Kenneth Casso... | adding names to array signals |
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2020-09-12 |
Luke Kenneth Casso... | whoops, indentation error |
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2020-09-12 |
Luke Kenneth Casso... | enable Display debugs |
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2020-09-12 |
Luke Kenneth Casso... | set bytesel in dcache store |
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2020-09-11 |
Luke Kenneth Casso... | separat stbs_done into ld/st |
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2020-09-11 |
Luke Kenneth Casso... | dcache load/store test |
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2020-09-11 |
Luke Kenneth Casso... | debugging dcache |
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2020-09-11 |
Luke Kenneth Casso... | wrong width for data / addr |
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2020-09-11 |
Luke Kenneth Casso... | connect up WB SRAM to dcache test |
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2020-09-11 |
Luke Kenneth Casso... | start on dcache test |
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2020-09-11 |
Luke Kenneth Casso... | missing comb += |
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2020-09-11 |
Luke Kenneth Casso... | missing maybe_tlb_plrus |
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2020-09-11 |
Luke Kenneth Casso... | WAY_BITS not TLB_WAY_BITS |
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2020-09-11 |
Luke Kenneth Casso... | whoops new node not to be calculated at end |
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2020-09-11 |
Luke Kenneth Casso... | try to get better DTLBUpdate |
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2020-09-11 |
Luke Kenneth Casso... | simplify dcache pending |
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2020-09-11 |
Luke Kenneth Casso... | move dcache pending test to separate module |
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2020-09-11 |
Luke Kenneth Casso... | more error correction in dcache |
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2020-09-11 |
Luke Kenneth Casso... | use module for TLBUpdate |
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2020-09-11 |
Luke Kenneth Casso... | add brackets round if & in dcache |
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2020-09-11 |
Cole Poirier | icache.py add test_icache and icache_sim derived from... |
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2020-09-11 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-09-11 |
Cole Poirier | icache.py fix spelling, syntax |
tree | commitdiff |
2020-09-10 |
Luke Kenneth Casso... | simplify read/write pte |
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