add in privileged instruction decision-making in PowerDecode2
[soc.git] / src / soc / fu / compunits /
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... add bigendian flag
2020-07-11 Luke Kenneth Casso... add endian
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-10 Luke Kenneth Casso... re-add rc/oe back into LDST input record
2020-07-10 Luke Kenneth Casso... whew panic over, missed a bigendian argument in test_co...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py
2020-07-06 Luke Kenneth Casso... add mul compunit
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-06 Luke Kenneth Casso... sort out initialisation of TstL0CacheBuffer in ldst...
2020-07-05 Luke Kenneth Casso... check trap compunit output properly
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... check spr1 in test spr compunit
2020-07-05 Luke Kenneth Casso... add first spr compunit test (not working yet)
2020-07-05 Luke Kenneth Casso... comment out SPR for now, needs SPR regfile
2020-07-05 Luke Kenneth Casso... add SPR compunit
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... oops initialise Function Unit class with idx
2020-07-04 Luke Kenneth Casso... add first cookie-cut test_trap_compunit.py
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... name function unit ALUs
2020-07-02 Luke Kenneth Casso... comment out DIV unit for now
2020-07-02 Luke Kenneth Casso... add DIV function unit to compunits
2020-07-02 Luke Kenneth Casso... add trap function unit into compunits
2020-07-01 Luke Kenneth Casso... add in trap compunit
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... use while / exception in test_compunit loop
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth Casso... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth Casso... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth Casso... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output phase of test_alu_compunit.py
2020-06-07 Luke Kenneth Casso... add missing arg to ISA in test_compunit
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... work out how to initialise memory directly
2020-06-06 Luke Kenneth Casso... initialise L0 Memory from simulator memory
2020-06-06 Luke Kenneth Casso... wait a little for wr.rel to activate if wrmask is active
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-06-06 Luke Kenneth Casso... use name of unit to write simulator/vcd file
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth Casso... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth Casso... add beginnings of LDST compunit test
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... remove unneeded imports
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-04 Luke Kenneth Casso... connect up write-ports from Regfiles to FUs
2020-06-04 Luke Kenneth Casso... docstring for AllFunctionUnits
2020-06-04 Luke Kenneth Casso... connect up Function Unit operand subsets
2020-06-03 Luke Kenneth Casso... add a simple core, not intended for production use
2020-06-03 Luke Kenneth Casso... add a simple class containing all FunctionUnits
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... use common get_cu_inputs for CR unit tests
2020-06-03 Luke Kenneth Casso... convert shift_rot tests to use common get_cu_inputs...
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... reorganise ALU tests, move get_cu_inputs function to...
2020-06-03 Luke Kenneth Casso... worked out how to dynamically enable carry-in to ALU...
2020-06-03 Luke Kenneth Casso... correct overflow-enable flags for rdmask specs in ALU
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-03 Luke Kenneth Casso... move over to using power_regspec_map.py from PowerDecod...
2020-06-03 Luke Kenneth Casso... move obtaining simulator data into common function...
2020-06-02 Luke Kenneth Casso... argh - bad hack, detecting when there are no registers...
2020-06-02 Luke Kenneth Casso... take out unneeded code, add Settle() to see if it helps...
2020-06-02 Luke Kenneth Casso... hooray, get_cu_inputs now common to both types of tests
2020-06-02 Luke Kenneth Casso... remove unneeded variable
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR
2020-06-02 Luke Kenneth Casso... debugging branch fast registers
2020-06-02 Luke Kenneth Casso... add read-write register numbering detection
2020-06-02 Luke Kenneth Casso... whitespace
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... remove reading port 3 for CR pipeline. RS moved to...
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