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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / test / test_fsm.py
2021-04-23 Luke Kenneth Casso... whitespace blob | commitdiff | raw
2020-09-17 Jacob Lifshayreplace sim._state.timeline.now with sim._engine.now blob | commitdiff | raw | diff to current
2020-07-22 Jacob Lifshayfix test_div_state_fsm blob | commitdiff | raw | diff to current
2020-07-19 Luke Kenneth Casso... if nmigen.sim.pysim import fails use nmigen.back.pysim blob | commitdiff | raw | diff to current
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... blob | commitdiff | raw | diff to current
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests blob | commitdiff | raw | diff to current