comment inputs and outputs from ALU unit test
[soc.git] / src / soc / fu /
2020-05-31 Luke Kenneth Casso... comment inputs and outputs from ALU unit test
2020-05-31 Luke Kenneth Casso... imports - use of globals. baaaad
2020-05-31 Luke Kenneth Casso... remove unneeded code and inputs. convert to "naming...
2020-05-31 Luke Kenneth Casso... split out common code from test_alu_compunit.py
2020-05-31 Luke Kenneth Casso... de-hard-code-ify getting results from MultiCompUnit
2020-05-31 Luke Kenneth Casso... clarify
2020-05-31 Luke Kenneth Casso... OP_CMPEQB also requesting change of output reg (stop...
2020-05-31 Luke Kenneth Casso... OP_CMP is requesting a change of the output register...
2020-05-31 Luke Kenneth Casso... still investigating
2020-05-31 Luke Kenneth Casso... start with zero, try not to compare against 9 bytes...
2020-05-31 Luke Kenneth Casso... more debug statements
2020-05-31 Luke Kenneth Casso... add in more CR debug statements
2020-05-31 Luke Kenneth Casso... copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
2020-05-31 Luke Kenneth Casso... remove commented-out vars from ALU input record
2020-05-31 Luke Kenneth Casso... write cr0 when op.write_cr.ok is set
2020-05-31 Luke Kenneth Casso... add write_cr to ALU record subset
2020-05-31 Luke Kenneth Casso... comment out xer ov/so for now
2020-05-30 Luke Kenneth Casso... get carry from cr write_cr
2020-05-30 Luke Kenneth Casso... select CR0 write out only when RC=1
2020-05-30 Luke Kenneth Casso... set CR0 output when OP_CMP or OP_CMPEQB need it
2020-05-30 Luke Kenneth Casso... add in write-mask into MultiCompUnit and MCU-ALU unit...
2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-30 Luke Kenneth Casso... create read-mask for ALU CompUnit: switches off optiona...
2020-05-30 Luke Kenneth Casso... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth Casso... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth Casso... order of XER so/ca wrong way round from regspec
2020-05-29 Luke Kenneth Casso... module comments for popcount
2020-05-29 Luke Kenneth Casso... comments on popcount
2020-05-29 Luke Kenneth Casso... trigger read ALU ready/valid from latch as well
2020-05-28 Luke Kenneth Casso... move simple_popcount out of class (does not use any...
2020-05-28 Luke Kenneth Casso... extra check on rd.req in test_alu_compunit
2020-05-28 Michael NolanAdd proof for OP_SETB
2020-05-28 Michael NolanAdd OP_SETB
2020-05-28 Michael NolanFix test_isel to properly examine registers
2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-28 Luke Kenneth Casso... debug-print rd/wr rel in test_alu_compunit
2020-05-28 Luke Kenneth Casso... debugging test_alu_compunit.py
2020-05-28 Luke Kenneth Casso... start on a compunit ALU test
2020-05-28 Luke Kenneth Casso... update comment
2020-05-28 Luke Kenneth Casso... remove trick of not setting SO
2020-05-27 Luke Kenneth Casso... code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS
2020-05-27 Luke Kenneth Casso... add LD/ST pipe_data
2020-05-27 Luke Kenneth Casso... LogicalOutputData does not need XER.so
2020-05-27 Luke Kenneth Casso... comments
2020-05-27 Luke Kenneth Casso... remove XER.ca from logical Input Data - not needed
2020-05-27 Luke Kenneth Casso... cleanup logical main proof
2020-05-27 Luke Kenneth Casso... check cr0, ov and ca ok signals in ALU main_stage proof
2020-05-27 Luke Kenneth Casso... add carry-out, overflow and cr0 ok setting in ALU main_...
2020-05-27 Luke Kenneth Casso... add SRR0 to TrapInputData
2020-05-27 Luke Kenneth Casso... add links to bugreports into ALu formal proof as well
2020-05-27 Luke Kenneth Casso... add links to bugreports into alu output stage proof
2020-05-27 Luke Kenneth Casso... check reg output Data.ok in shift_rot formal proof
2020-05-27 Luke Kenneth Casso... rename CROutputData.cr_o to just CROutputData.cr
2020-05-27 Luke Kenneth Casso... test Data.ok for cr output and full cr output
2020-05-27 Luke Kenneth Casso... assign and test on Data, TODO add Data.ok checking...
2020-05-27 Michael NolanFix bug in alu main stage proof
2020-05-26 Michael NolanAdd extras from bottom of the file
2020-05-26 Michael NolanRewrite proof to be more in line with what appears...
2020-05-26 Luke Kenneth Casso... whitespace, add commentary
2020-05-25 Michael NolanCorrect polarity of shadow signal
2020-05-25 Luke Kenneth Casso... document shadown inversion
2020-05-25 Michael NolanAdd link to compunit wiki page
2020-05-25 Michael NolanCorrect property numbers, add assertions about busy
2020-05-25 Michael NolanAdd assertions about go_wr and wr_rel
2020-05-25 Michael NolanMinor cleanup of comments
2020-05-25 Michael NolanBegin working on proof for compunit/fu
2020-05-25 Luke Kenneth Casso... add zero immed on LDST, untested
2020-05-24 Luke Kenneth Casso... add comments for SPR pipe_data
2020-05-24 Luke Kenneth Casso... add SPR pipe_data.py
2020-05-24 Luke Kenneth Casso... over 80 char limit
2020-05-24 Luke Kenneth Casso... add test of reg output, for MFCRF and ISEL
2020-05-24 Luke Kenneth Casso... add gitignore for branch fu formal
2020-05-24 Luke Kenneth Casso... add OP_CMPB formal proof
2020-05-24 Michael NolanAssert that ctr is only written when needed
2020-05-24 Luke Kenneth Casso... split out Popcount into separate module: visually it...
2020-05-24 Luke Kenneth Casso... copy code for MTMSR from microwatt into comments
2020-05-24 Luke Kenneth Casso... add links for trap main stage
2020-05-24 Luke Kenneth Casso... add untested OP_MTMSR and OP_MFMSR
2020-05-24 Luke Kenneth Casso... comment and add links to branch formal proof
2020-05-24 Luke Kenneth Casso... add copy of bpermd proof to logical formal proof (not...
2020-05-24 Luke Kenneth Casso... track down overwrite of variable b
2020-05-24 Michael NolanFix proof of bpermd module
2020-05-24 Michael NolanFix bpermd and make tests pass
2020-05-24 Michael NolanFix test_pipe_caller to conform to new Data() interface...
2020-05-24 Luke Kenneth Casso... comments on branch pipeline
2020-05-24 Luke Kenneth Casso... convert CR pipeline to Data.ok
2020-05-24 Luke Kenneth Casso... convert ALU to output Data on int reg
2020-05-24 Luke Kenneth Casso... convert logical to output Data on int reg
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-24 Luke Kenneth Casso... cleanup/code-munge on ALU main stage proof
2020-05-24 Luke Kenneth Casso... error in alu output stage formal proof setup
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-24 Luke Kenneth Casso... spelling mistake in variable
2020-05-24 Luke Kenneth Casso... TODO mention OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth Casso... add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
2020-05-23 colepoirierAdded branch and shift_rot imports to fu/compunits...
2020-05-23 Luke Kenneth Casso... add input / output stage missing modules
2020-05-23 Luke Kenneth Casso... update docs on compunits
2020-05-23 Luke Kenneth Casso... remove extraneous test_isel
2020-05-23 Luke Kenneth Casso... document purpose of regspec module
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