2020-07-06 |
Luke Kenneth Casso... | investigating mul pipeline |
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2020-07-06 |
Luke Kenneth Casso... | first cut at mul test pipeline |
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2020-07-06 |
Luke Kenneth Casso... | add first cut at fu mul pipeline |
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2020-07-06 |
Luke Kenneth Casso... | adding mtspr tests |
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2020-07-06 |
Luke Kenneth Casso... | adding OP_MTMSR test |
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2020-07-06 |
Luke Kenneth Casso... | sort out initialisation of TstL0CacheBuffer in ldst... |
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2020-07-05 |
Luke Kenneth Casso... | add mtmsr tests (fail) |
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2020-07-05 |
Luke Kenneth Casso... | check trap compunit output properly |
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2020-07-05 |
Luke Kenneth Casso... | check msr in trap test, fix OP_RFID |
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2020-07-05 |
Luke Kenneth Casso... | add an illegal instruction trap test |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-05 |
Luke Kenneth Casso... | check xer_out not xer_in |
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2020-07-05 |
Luke Kenneth Casso... | sigh read and write xer detection, fix spr and trap... |
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2020-07-05 |
Luke Kenneth Casso... | check spr1 in test spr compunit |
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2020-07-05 |
Luke Kenneth Casso... | get/set slow spr in spr test_pipe_caller |
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2020-07-05 |
Luke Kenneth Casso... | add first spr compunit test (not working yet) |
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2020-07-05 |
Luke Kenneth Casso... | comment out SPR for now, needs SPR regfile |
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2020-07-05 |
Luke Kenneth Casso... | add SPR compunit |
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2020-07-05 |
Luke Kenneth Casso... | check NIA on trap fu test |
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2020-07-04 |
Luke Kenneth Casso... | cater for illegal instruction (generates a trap) |
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2020-07-04 |
Luke Kenneth Casso... | add sc back in |
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2020-07-04 |
Luke Kenneth Casso... | comments in trap about exceptions using microcoding |
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2020-07-04 |
Luke Kenneth Casso... | more updating spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | more updating spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | rename spr1/spr2 to fast1/fast2 in branch |
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2020-07-04 |
Luke Kenneth Casso... | update trap docstring |
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2020-07-04 |
Luke Kenneth Casso... | use new consts module |
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2020-07-04 |
Luke Kenneth Casso... | sorting out trap fastregs |
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2020-07-04 |
Luke Kenneth Casso... | sort out trap test reg checking |
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2020-07-04 |
Luke Kenneth Casso... | rename spr1 to fast1 in trap data |
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2020-07-04 |
Luke Kenneth Casso... | sorting out fast/spr naming |
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2020-07-04 |
Luke Kenneth Casso... | oops initialise Function Unit class with idx |
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2020-07-04 |
Luke Kenneth Casso... | add first cookie-cut test_trap_compunit.py |
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2020-07-04 |
Luke Kenneth Casso... | debugging decoding of SPRs (fast) |
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2020-07-04 |
Luke Kenneth Casso... | add spr test, add decode of spr in/out |
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2020-07-04 |
Luke Kenneth Casso... | add spr main stage |
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2020-07-04 |
Luke Kenneth Casso... | add spr input record |
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2020-07-04 |
Luke Kenneth Casso... | add SPR pipeline |
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2020-07-04 |
Luke Kenneth Casso... | reduce steps per stage to 8 |
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2020-07-03 |
Luke Kenneth Casso... | set only div/rem supported |
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2020-07-02 |
Luke Kenneth Casso... | allow flexible selection of the types of ALUs |
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2020-07-02 |
Luke Kenneth Casso... | fix unit tests due to change in using pspec |
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2020-07-02 |
Luke Kenneth Casso... | allow ALU names to propagate through from FU to CompUni... |
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2020-07-02 |
Luke Kenneth Casso... | name function unit ALUs |
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2020-07-02 |
Luke Kenneth Casso... | comment out DIV unit for now |
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2020-07-02 |
Luke Kenneth Casso... | increase combinatorial stages to 8 |
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2020-07-02 |
Luke Kenneth Casso... | reduce DIV radix to 1 |
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2020-07-02 |
Luke Kenneth Casso... | add DIV function unit to compunits |
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2020-07-02 |
Luke Kenneth Casso... | add trap function unit into compunits |
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2020-07-01 |
Luke Kenneth Casso... | whoops missed some cases in unit test changing ALUHelpers |
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2020-07-01 |
Luke Kenneth Casso... | whoops swapped trap test instructions accidentally |
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2020-07-01 |
Luke Kenneth Casso... | attempting to add SPRs to rfid test |
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2020-07-01 |
Luke Kenneth Casso... | trap test check results |
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2020-07-01 |
Luke Kenneth Casso... | add in trap compunit |
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2020-07-01 |
Luke Kenneth Casso... | add rfid and td/tw trap test |
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2020-07-01 |
Luke Kenneth Casso... | continue debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | start running trap unit test, fixing errors |
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2020-06-30 |
Luke Kenneth Casso... | code-morph on div pipeline |
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2020-06-29 |
Luke Kenneth Casso... | add README for fu directory |
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2020-06-29 |
Luke Kenneth Casso... | use correct ALUHelpers in div test |
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2020-06-29 |
Luke Kenneth Casso... | sort out syntax errors in div |
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2020-06-29 |
Luke Kenneth Casso... | first unit test for div |
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2020-06-28 |
Luke Kenneth Casso... | got Pi2LSUI FSM working |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | make Memory accessible via TestSRAMBareLoadStoreUnit |
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2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
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2020-06-22 |
Luke Kenneth Casso... | simplified L0CacheBuffer down to a "PortInterface Arbiter" |
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2020-06-19 |
Luke Kenneth Casso... | whitespace update |
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2020-06-18 |
Jacob Lifshay | div pipe completed except for tests |
tree | commitdiff |
2020-06-18 |
Jacob Lifshay | finish code to calculate the 64-bit output of the div... |
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2020-06-18 |
Jacob Lifshay | actually remove todo comment for manually checking... |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-18 |
Jacob Lifshay | fix bug and manually check div overflow code against... |
tree | commitdiff |
2020-06-18 |
Luke Kenneth Casso... | use while / exception in test_compunit loop |
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2020-06-18 |
Jacob Lifshay | working on adding rest of stage classes for div pipeline |
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2020-06-17 |
Luke Kenneth Casso... | decoding assembly instruction name, move to separate... |
tree | commitdiff |
2020-06-17 |
Luke Kenneth Casso... | get fu compunit test to use ISACaller instruction-memory |
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2020-06-17 |
Luke Kenneth Casso... | start to add in independent execution into ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | use an independent power decoder in ISACaller |
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2020-06-16 |
Luke Kenneth Casso... | update popcount docstring |
tree | commitdiff |
2020-06-15 |
Luke Kenneth Casso... | move setup/check memory into helper functions for use... |
tree | commitdiff |
2020-06-15 |
Luke Kenneth Casso... | whoops LDSTCompUnit was identified as a Function.ALU... |
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2020-06-15 |
Luke Kenneth Casso... | add in TstL0CacheBuffer but disable temporarily |
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2020-06-14 |
Luke Kenneth Casso... | add optional LDSTFunctionUnit to compunits |
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2020-06-14 |
Luke Kenneth Casso... | unit tests showing byte-reverse works |
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2020-06-14 |
Luke Kenneth Casso... | reasonably certain that the careful and slow use of... |
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2020-06-12 |
Luke Kenneth Casso... | update ld/st test to see what is going on |
tree | commitdiff |
2020-06-12 |
Luke Kenneth Casso... | tracking down what looks like an error in the Simulator... |
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2020-06-12 |
Luke Kenneth Casso... | debug printout of sim and hardware memory, shows mismat... |
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2020-06-12 |
Luke Kenneth Casso... | use ALUHelpers in LDSTCompUnit test |
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2020-06-11 |
Luke Kenneth Casso... | some ugly hacks that get LD/ST immediate working |
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2020-06-11 |
Luke Kenneth Casso... | even more complexity in CompALUMulti, to deal with... |
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2020-06-11 |
Luke Kenneth Casso... | must distinguish between rd/write xer_ca sim helpers |
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2020-06-11 |
Luke Kenneth Casso... | fixing get_rd_sim_xer_ca, has to only read carry if... |
tree | commitdiff |
2020-06-11 |
Luke Kenneth Casso... | yield needed for unit tests to work (has to go) |
tree | commitdiff |
2020-06-11 |
Luke Kenneth Casso... | read and write version of get_sim_xer_ca are different |
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2020-06-11 |
Luke Kenneth Casso... | use ALUHelpers in shift_rot |
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2020-06-11 |
Luke Kenneth Casso... | add fast spr1/2 sim ALUHelpers |
tree | commitdiff |
2020-06-11 |
Luke Kenneth Casso... | rename get_sim_cr_a to get_wr_sim_cr_a for now |
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2020-06-10 |
Luke Kenneth Casso... | whitespace |
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next |