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read MSR.PR and MSR.DR and update ICache priv/virt moed during fetch
[soc.git]
/
src
/
soc
/
interrupts
/
2020-11-22
Luke Kenneth Casso...
simplify litex-core wishbone interfaces
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
hmmm XICS data being asserted on wb bus for too long
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
argh missed a VHDL "&" translating to Cat
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
reduce XICS address lookup by 2 bits
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
whoops, combinatorial loop on pending_priority
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
XICS addresses in words: divide by 4
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
move wb read/write to separate util test library and...
tree
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commitdiff
2020-09-04
Luke Kenneth Casso...
adding option to include XICS external interrupts.
tree
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commitdiff
2020-07-30
Luke Kenneth Casso...
ha! found source of XICS test bug: wishbone stb was...
tree
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commitdiff
2020-07-29
Luke Kenneth Casso...
more exploratory testing of XICS, joining ICP and ICS...
tree
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commitdiff
2020-07-29
Luke Kenneth Casso...
start on test joining XICS ICS to ICP
tree
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commitdiff
2020-07-29
Luke Kenneth Casso...
tidyup XICS, identify (potential?) bug?
tree
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commitdiff
2020-07-29
Jacob Lifshay
add __init__.py to all source directories
tree
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commitdiff
2020-07-28
Luke Kenneth Casso...
add preliminary investigative test of XICS ICS
tree
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commitdiff
2020-07-27
Luke Kenneth Casso...
add 2nd part of XICS interrupt interface
tree
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commitdiff
2020-07-26
Luke Kenneth Casso...
start on conversion of xics.vhdl to nmigen
tree
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commitdiff