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Fix test breakage in MUL proofs
[soc.git] / src / soc / litex /
2020-08-29 Luke Kenneth Casso... break down XER into flags tree | commitdiff
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py tree | commitdiff
2020-08-29 Luke Kenneth Casso... investigating CR mtocrf / mfocrf tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Luke Kenneth Casso... add way to capture CR from DMI in litex sim tree | commitdiff
2020-08-24 Luke Kenneth Casso... argh, reading regfile over DMI was overlapped and corru... tree | commitdiff
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-23 Luke Kenneth Casso... add algebraic ld tests lwax, lwaux tree | commitdiff
2020-08-23 Luke Kenneth Casso... add in DMI "stat" loop which monitors core "stopping" tree | commitdiff
2020-08-23 Luke Kenneth Casso... comment why litex sim mem map is altered tree | commitdiff
2020-08-22 Luke Kenneth Casso... load bios not 1.bin unit test tree | commitdiff
2020-08-22 Luke Kenneth Casso... add means to run microwatt test binaries tree | commitdiff
2020-08-22 Luke Kenneth Casso... investigating litex sdrinit function tree | commitdiff
2020-08-21 Luke Kenneth Casso... testing 64-bit wishbone bus after 32-bit *still* fails... tree | commitdiff
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus tree | commitdiff
2020-08-17 Luke Kenneth Casso... move Mask to nmutil tree | commitdiff
2020-08-17 Luke Kenneth Casso... use longer memtest in litex sim tree | commitdiff
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest tree | commitdiff
2020-08-16 Luke Kenneth Casso... limit debug reporting in litex sim to range of pc tree | commitdiff
2020-08-15 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-15 Luke Kenneth Casso... thanks to daveshah, added simulation of dram tree | commitdiff
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-08-05 Luke Kenneth Casso... rename ibus/dbus (shorten) tree | commitdiff
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-05 Luke Kenneth Casso... adding bus data width of 64 in litex sim doesnt work tree | commitdiff
2020-08-04 Luke Kenneth Casso... cycle through INT regs, read and debug in litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... single-step and print out PC using DMI in litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... get litex sim to kick off a "STEP" via the DMI interfac... tree | commitdiff
2020-08-04 Luke Kenneth Casso... connect up a DMI FSM to litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... more remove wildcard imports tree | commitdiff
2020-08-04 Luke Kenneth Casso... do not use wildcard imports tree | commitdiff
2020-08-04 Luke Kenneth Casso... adding litex sim experimentation. tree | commitdiff
2020-07-23 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting tree | commitdiff
2020-07-23 Luke Kenneth Casso... try SDRAM SDR tree | commitdiff
2020-07-23 Luke Kenneth Casso... try different MEMTEST_xxx sizes with 64 bit bus width tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Luke Kenneth Casso... re-add CRG (clock reset generator) tree | commitdiff
2020-07-22 Luke Kenneth Casso... add clock domain using snippet taken from random file tree | commitdiff
2020-07-22 Luke Kenneth Casso... cleanup in litex core.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... update comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add dummy irq set/get tree | commitdiff
2020-07-22 Luke Kenneth Casso... add boot-helper.S etc from microwatt litex core tree | commitdiff
2020-07-22 Luke Kenneth Casso... missed import of Builder, set cpu_type to "None" tempor... tree | commitdiff
2020-07-22 Luke Kenneth Casso... begin converting litex sim to libre-soc tree | commitdiff
2020-07-22 Luke Kenneth Casso... do not use wildcard import tree | commitdiff
2020-07-22 Luke Kenneth Casso... start from vexriscv sim.py from tree | commitdiff
2020-07-22 Luke Kenneth Casso... correct syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... first version of litex core (to be submitted upstream... tree | commitdiff