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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
minerva
/
units
/ fetch.py
2021-08-24
Luke Kenneth Casso...
big rename, global/search/replace of ready_o with o_rea...
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2020-10-22
Luke Kenneth Casso...
add detection and disable of Instruction Wishbone based...
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2020-07-30
Luke Kenneth Casso...
set sel line in minerva instruction fetch
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2020-07-23
Luke Kenneth Casso...
allow imem to be 64/32 bit wide
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Luke Kenneth Casso...
sigh easier to just do a line-for-line comparison of...
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Luke Kenneth Casso...
port minerva cache fixes
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2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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2020-07-01
Luke Kenneth Casso...
minor reorg on how Bus and Config classes are set up
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2020-06-29
Luke Kenneth Casso...
fetch instructions from bare wishbone fetch unit
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2020-06-28
Luke Kenneth Casso...
add cached fetch unit pass-through args
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2020-06-28
Luke Kenneth Casso...
need args to WishboneArbiter, match data width size
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2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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2020-06-28
Luke Kenneth Casso...
parameterise minerva i-cache
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2020-06-26
Luke Kenneth Casso...
whitespace and imports
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2020-06-26
Luke Kenneth Casso...
whitespace
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2020-03-11
Luke Kenneth Casso...
fix more imports
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2020-03-11
Luke Kenneth Casso...
dewildcardify units
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2020-03-11
Luke Kenneth Casso...
add minerva source from https://github.com/lambdaconcep...
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