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Rename the internal DFF of latchregisters to avoid conflict
[soc.git]
/
src
/
soc
/
2020-05-24
Cesar Strauss
Rename the internal DFF of latchregisters to avoid...
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
add gitignore for branch fu formal
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
add OP_CMPB formal proof
tree
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commitdiff
2020-05-24
Michael Nolan
Assert that ctr is only written when needed
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commitdiff
2020-05-24
Luke Kenneth Casso...
split out Popcount into separate module: visually it...
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
copy code for MTMSR from microwatt into comments
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commitdiff
2020-05-24
Luke Kenneth Casso...
add links for trap main stage
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commitdiff
2020-05-24
Luke Kenneth Casso...
add untested OP_MTMSR and OP_MFMSR
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commitdiff
2020-05-24
Luke Kenneth Casso...
add MFMSR and MTMSRD enums to Function
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commitdiff
2020-05-24
Luke Kenneth Casso...
comment and add links to branch formal proof
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commitdiff
2020-05-24
Luke Kenneth Casso...
add copy of bpermd proof to logical formal proof (not...
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
track down overwrite of variable b
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commitdiff
2020-05-24
Michael Nolan
Fix proof of bpermd module
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commitdiff
2020-05-24
Michael Nolan
Fix bpermd and make tests pass
tree
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commitdiff
2020-05-24
Michael Nolan
Fix test_pipe_caller to conform to new Data() interface...
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commitdiff
2020-05-24
Luke Kenneth Casso...
add stub regfiles.py
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commitdiff
2020-05-24
Luke Kenneth Casso...
hmm...
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commitdiff
2020-05-24
Luke Kenneth Casso...
add very rapid DummyALU for test purposes in MultiCompUnit
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
comments on branch pipeline
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commitdiff
2020-05-24
Luke Kenneth Casso...
convert CR pipeline to Data.ok
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
convert ALU to output Data on int reg
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commitdiff
2020-05-24
Luke Kenneth Casso...
convert logical to output Data on int reg
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commitdiff
2020-05-24
Luke Kenneth Casso...
start using Data in pipelines
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commitdiff
2020-05-24
Luke Kenneth Casso...
cleanup/code-munge on ALU main stage proof
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
error in alu output stage formal proof setup
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
output registers need to be Data type (consistently)
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commitdiff
2020-05-24
Luke Kenneth Casso...
spelling mistake in variable
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commitdiff
2020-05-24
Luke Kenneth Casso...
TODO mention OP_MTMSR/OP_MFMSR
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
tree
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commitdiff
2020-05-24
Luke Kenneth Casso...
move docstring to wiki for compunit
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commitdiff
2020-05-23
colepoirier
Added branch and shift_rot imports to fu/compunits...
tree
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commitdiff
2020-05-23
Cesar Strauss
Add a few test cases with zero_a set, in combination...
tree
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commitdiff
2020-05-23
Cesar Strauss
Allow zero_a to be set when simulating an operation
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add input / output stage missing modules
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
common function for op zero and op immed
tree
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commitdiff
2020-05-23
Cesar Strauss
Choose between RA (src1) and zero immediate, conditione...
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commitdiff
2020-05-23
Luke Kenneth Casso...
update docs on compunits
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commitdiff
2020-05-23
Luke Kenneth Casso...
remove extraneous test_isel
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commitdiff
2020-05-23
Luke Kenneth Casso...
add comments
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
document purpose of regspec module
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commitdiff
2020-05-23
Luke Kenneth Casso...
split out RegSpecs into separate module
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commitdiff
2020-05-23
Luke Kenneth Casso...
add TODO on multi-in multi-out Function Units
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
split out RegSpec API into separate class (TODO: move...
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add notes on FunctionUnit API
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commitdiff
2020-05-23
Luke Kenneth Casso...
make MultiCompUnit and testing ALU use regspec API...
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
remove unneeded imports
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commitdiff
2020-05-23
Luke Kenneth Casso...
make demo/test ALU look like nmigen pipeline API
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commitdiff
2020-05-23
Luke Kenneth Casso...
add stub DataMerger class
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commitdiff
2020-05-23
Luke Kenneth Casso...
add link to regspecs on wiki
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add regspec capability to MultiCompUnit
tree
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commitdiff
2020-05-23
Michael Nolan
Modify proof of isel to use full CR register
tree
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commitdiff
2020-05-23
Michael Nolan
Add test_isel
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
make immediate-or-RA selection optional based on awaren...
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
start to morph MultiCompUnit to take "regspec" as the...
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add CR_ISEL formal proof to CR pipeline
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add CR_ISEL (and unit test) to CR pipeline
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add gitignore
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
CR field on Br input data is specd as 0:3 range
tree
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commitdiff
2020-05-23
Luke Kenneth Casso...
add b to CR pipe input data, for isel
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
add TODO and link to SHIFT_ROT formal bugreport
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove xer.so from ShiftRot formal proof
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove sticky overflow from Shift Rot pipeline
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commitdiff
2020-05-22
Luke Kenneth Casso...
test branch ctr ok flag
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commitdiff
2020-05-22
Luke Kenneth Casso...
cleaner way to test link register ok
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commitdiff
2020-05-22
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-05-22
Michael Nolan
Fix link handling in branch proof
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
variable-name munging for branch formal
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commitdiff
2020-05-22
Michael Nolan
Add formal proof for branch unit, fix bug with bcreg
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
cleanup logical pipe formal proof
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
split out Logical Input and Output stages to common...
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
div probably uses ALU not Logical, needs double-checkin...
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
update comments for ALUCompUnit
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
soc.fu.logical.input_stage no different from ALU: delete
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
covert ALU FU to CommonInputStage
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
create common input pipe spec to avoid code-duplication
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
move CR over to CompCROpSubset
tree
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commitdiff
2020-05-22
Michael Nolan
Convert branch unit to new CR interface
tree
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commitdiff
2020-05-22
Michael Nolan
Complete CR proof
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
increase fu-fu test matrix size
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove unneeded code
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
rename ShiftRot to Mul in fu mul test
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
rename Logical to Div in fu div test
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
cookie-cut start on div pipe
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commitdiff
2020-05-22
Luke Kenneth Casso...
add cookie-cut mul pipeline template
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
over 80 chars
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
comment tidyup
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
use CompBROpSubset and reduce it down in size (remove...
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
code-shuffle
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove accidentally added branch input stage
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commitdiff
2020-05-22
Tobias Platen
fix ModuleNotFoundError
tree
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commitdiff
2020-05-21
Luke Kenneth Casso...
add fu logical_input_record.py
tree
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commitdiff
2020-05-21
Luke Kenneth Casso...
update CROutputData to use Data()
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commitdiff
2020-05-21
Luke Kenneth Casso...
update comments
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commitdiff
2020-05-21
Luke Kenneth Casso...
whitespace cleanup
tree
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commitdiff
2020-05-21
Luke Kenneth Casso...
whitespace cleanup
tree
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commitdiff
2020-05-21
Luke Kenneth Casso...
remove input_cr, output_cr and is_32bit from CompCROpSubset
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commitdiff
2020-05-21
Luke Kenneth Casso...
add read_cr_whole and write_cr_whole to CompCROpSubset
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commitdiff
2020-05-21
Luke Kenneth Casso...
add first cut at cr_input_record.py
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