whitespace and minor cleanup of D-Cache
[soc.git] / src /
2021-12-05 Luke Kenneth Casso... whitespace and minor cleanup of D-Cache
2021-12-05 Luke Kenneth Casso... more use of TLBHit Record in D-Cache
2021-12-05 Luke Kenneth Casso... correct tlb_hit_way and index sizes, use TLBHit Record...
2021-12-05 Luke Kenneth Casso... use TLBRecord in D-Cache for which TLB is selected
2021-12-05 Luke Kenneth Casso... split out TLBRecord, correct number of valid bits
2021-12-05 Luke Kenneth Casso... use Record in DCache for TLB
2021-12-05 Luke Kenneth Casso... use Record in D-Cache Cache Tags
2021-12-05 Luke Kenneth Casso... whitespace
2021-12-05 Luke Kenneth Casso... use Record for I-Cache Cache Tag/Valid
2021-12-05 Luke Kenneth Casso... whitespace
2021-12-05 Luke Kenneth Casso... use Record for ICache TLB
2021-12-05 Luke Kenneth Casso... sorting out test_mmu_dcache.py to use wb_get
2021-12-05 Luke Kenneth Casso... convert icache.py to standard wishbone Interface
2021-12-05 Luke Kenneth Casso... fake up wishbone stall signal in icache.
2021-12-05 Luke Kenneth Casso... fix icache row store issue
2021-12-05 Luke Kenneth Casso... using same tag/row functions as in dcache.py
2021-12-05 Luke Kenneth Casso... more signal sizes in icache.py
2021-12-05 Luke Kenneth Casso... incorrect Signal sizes in icache.py,
2021-12-05 Luke Kenneth Casso... sorting out icache.py, used to work
2021-12-05 Luke Kenneth Casso... remove redundant code
2021-12-05 Luke Kenneth Casso... add I-Cache standard bus (not used yet)
2021-12-05 Luke Kenneth Casso... remove yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth Casso... replace yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth Casso... wishbone bus convert on dcache
2021-12-05 Luke Kenneth Casso... correct import of wg_get function
2021-12-04 Luke Kenneth Casso... remove yet another duplicated copy of wb_get and add...
2021-12-04 Luke Kenneth Casso... rename function which needs replacing
2021-12-04 Luke Kenneth Casso... should have been using common version of wb_get, not...
2021-12-04 Luke Kenneth Casso... should not have been duplicating wb_get function in...
2021-12-04 Luke Kenneth Casso... get test_mmu_dcache.py working again
2021-12-04 Luke Kenneth Casso... remove wb_get, should not have been duplicated
2021-12-04 Luke Kenneth Casso... remove wb_get, should not have been massively duplicate...
2021-12-04 Luke Kenneth Casso... fix return results from pi_ld
2021-12-04 Luke Kenneth Casso... wark-wark, broke mmu with removing rin. reverted
2021-12-04 Tobias Platenfixed wait_addr to exit immediately on exception
2021-12-04 Luke Kenneth Casso... tidyup, comments
2021-12-04 Luke Kenneth Casso... tidyup mmu
2021-12-04 Luke Kenneth Casso... sigh in MMU FSM use direct access to ldst.dar/dsisr...
2021-12-04 Luke Kenneth Casso... remove DAR from PortInterface (where is the data going...
2021-12-04 Luke Kenneth Casso... stop using dar_o from PortInterface, get DAR directly...
2021-12-04 Luke Kenneth Casso... put DSISR and DAR publicly accessible in LoadStore1
2021-12-04 Luke Kenneth Casso... whoops fix up exception happened if alignment triggers...
2021-12-04 Luke Kenneth Casso... fix pi_st which should not be trying to wait for the...
2021-12-04 Luke Kenneth Casso... fixing DAR updating from exceptions
2021-12-04 Luke Kenneth Casso... whoops
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-04 Luke Kenneth Casso... store DAR in LoadStore1
2021-12-04 Luke Kenneth Casso... not busy if excrption occurs on MMU_LOOKUP in loadstore.py
2021-12-04 Luke Kenneth Casso... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth Casso... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth Casso... in loadstore.py set align_intr from request which comes...
2021-12-03 Luke Kenneth Casso... driver conflict on priv_mode and virt_mode, do not...
2021-12-03 Luke Kenneth Casso... fix up test_loadstore1.py
2021-12-03 Luke Kenneth Casso... in loadstore.py, when an exception is done or if the FSM
2021-12-03 Luke Kenneth Casso... fix PortInterfaceBase
2021-12-03 Luke Kenneth Casso... fix up LDST test functions pi_ld and pi_st to respect...
2021-12-03 Luke Kenneth Casso... whitespace
2021-12-03 Luke Kenneth Casso... add misaligned ld/st to trigger an exception
2021-12-03 Luke Kenneth Casso... comment out dsisr and dar in mmu FSM for now
2021-12-02 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-12-02 Tobias Platencleanup test_compldst_multi_mmu.py
2021-12-02 Luke Kenneth Casso... add a bitvector remap function, the plan is to use...
2021-12-02 Tobias Platenfix test_random in test_loadstore1
2021-12-02 Luke Kenneth Casso... use new namedtuple in core when calling regspec_decode()
2021-12-02 Luke Kenneth Casso... add module parameter to regspec_decode and therefore...
2021-12-02 Jacob Lifshayremove bitmanip fu cuz ternlogi (the only instruction...
2021-12-02 Jacob Lifshayadd ternlogi to shiftrot
2021-12-02 Jacob Lifshayformat code
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth Casso... experimenting with option to shorten MultiCompUnit...
2021-12-01 Luke Kenneth Casso... create single-stage ALU pipeline, shorten latency on...
2021-12-01 Luke Kenneth Casso... allow MultiCompUnit to set read and write latches to...
2021-12-01 Luke Kenneth Casso... FunctionUnitBaseMulti which derives from ReservationSta...
2021-12-01 Luke Kenneth Casso... better name for read latch in core.py
2021-12-01 Luke Kenneth Casso... use m.submodules[name] instead of getattr
2021-12-01 Luke Kenneth Casso... remove redundant / mis-named variable in core
2021-12-01 Luke Kenneth Casso... code-comments
2021-12-01 Luke Kenneth Casso... remove unneeded data structure in core
2021-12-01 Luke Kenneth Casso... whoops treereduce on write-vector set/clr error
2021-12-01 Luke Kenneth Casso... more code-cleanup
2021-12-01 Luke Kenneth Casso... use new regspec_decode and fu.get_iospec functions
2021-12-01 Luke Kenneth Casso... core tidyup
2021-12-01 Luke Kenneth Casso... add Regspecs get_io_spec function
2021-11-30 Luke Kenneth Casso... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias Platenrandom loadstore1 test: readback written data
2021-11-30 Tobias Platenreenable dcbz test case
2021-11-30 Tobias Platenreturn correct data from microwatt
2021-11-30 Tobias Platencleanup test_loadstore1.py
2021-11-30 Tobias Platenloadstore: add done_delay
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth Casso... add LogicalTestCases back in to test_core.py (pass)
2021-11-30 Luke Kenneth Casso... let PowerDecode2 decide which operand class to use...
2021-11-30 Luke Kenneth Casso... use latched readflag (recspec_decode_read "ok") instead...
2021-11-30 Luke Kenneth Casso... tidyup on read-flag latches
2021-11-30 Luke Kenneth Casso... fix read-decode information by latching not just the...
2021-11-30 Luke Kenneth Casso... fix write-after-write hazard checking
2021-11-30 Luke Kenneth Casso... allow busy to settle before checking state in test_core.py
2021-11-30 Luke Kenneth Casso... only check regs right at the end in test_core.py overla...
2021-11-30 Luke Kenneth Casso... move sim call before core run in test_core.py
2021-11-30 Luke Kenneth Casso... getting formerly unused test_core.py operational
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