fix bigint shift tests
[openpower-isa.git] / src /
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... minor cleanup in ISACaller on result handling
2022-10-01 Luke Kenneth Casso... simplify ISACaller execute_one
2022-10-01 Luke Kenneth Casso... simplify setting default SVSHAPE SPRs to zero
2022-10-01 Jacob Lifshayincrease pcdec. output compression by skipping impossib...
2022-09-30 Jacob Lifshayprefix codes tests pass
2022-09-30 Luke Kenneth Casso... ctr mode not needed, just use unconditional CTR dec
2022-09-30 Luke Kenneth Casso... set srcstep/dststep to zero in StepLoop (ISACaller...
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... comments/variables-cleanup
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... add sv.bc/vs - VLset - test. truncates VL at the vector...
2022-09-30 Luke Kenneth Casso... add new sv.bc CTR-loop test, subtracts VL from CTR
2022-09-30 Luke Kenneth Casso... whitespace
2022-09-30 Luke Kenneth Casso... use regs variables in get_predint
2022-09-30 Luke Kenneth Casso... comments
2022-09-30 Jacob Lifshayfix pcdec. assembly -- merge into va_form() since it...
2022-09-30 Jacob Lifshayrewrite pcdec. pseudocode to work better for JPEG
2022-09-30 Jacob Lifshayadd lookup table generation for JPEG decode
2022-09-30 Jacob Lifshayallow logging function to be overridden for Mem.log_fancy
2022-09-29 Jacob Lifshayconvert svp64 bigint unittests to use TestAccumulatorBase
2022-09-29 Jacob Lifshayfinish changing to use adde, not addeo for bigint add
2022-09-29 Luke Kenneth Casso... sv.adde not sv.addeo
2022-09-29 Luke Kenneth Casso... destination for maddedu and divmod2du for RS defaults...
2022-09-29 Luke Kenneth Casso... wowser, complex. implementing maddedu implicit RC/RS...
2022-09-29 Luke Kenneth Casso... add carry-roll-over-vector-mul-with-add (!) unit test
2022-09-29 Luke Kenneth Casso... comments
2022-09-29 Luke Kenneth Casso... add shift-left and shift-right scalar-to-vector tests
2022-09-29 Luke Kenneth Casso... update iterators in ISACaller, not used yet
2022-09-29 Jacob Lifshayrename madded->maddedu for consistency with PowerISA...
2022-09-29 Jacob Lifshayrename divrem2du->divmod2du for consistency with PowerI...
2022-09-29 Jacob Lifshayadd bigint tests and fix madded pseudocode
2022-09-29 Jacob Lifshayadd bigint ops
2022-09-29 Jacob Lifshayadd missing DRAFT comment
2022-09-29 Jacob Lifshayfix test_minor_30
2022-09-29 Jacob Lifshayformat code
2022-09-29 Jacob Lifshayremove unnecesary commented code
2022-09-28 Luke Kenneth Casso... srcstep
2022-09-28 Luke Kenneth Casso... rename iterators init function
2022-09-28 Luke Kenneth Casso... redundant comment
2022-09-28 Luke Kenneth Casso... split out svstate update in ISACaller
2022-09-28 Luke Kenneth Casso... move failfirst check to separate function in ISACaller
2022-09-28 Luke Kenneth Casso... add limit argument to MASK() helper
2022-09-28 Luke Kenneth Casso... bugfix reset remaps and get subvl early
2022-09-28 Luke Kenneth Casso... comments on horizontal-or
2022-09-28 Luke Kenneth Casso... make matrix horizontal-remap example more generic
2022-09-28 Luke Kenneth Casso... add horizontal-or-reduction example that thoroughly...
2022-09-28 Jacob Lifshayextracting demo JPEG bitstream works
2022-09-27 Luke Kenneth Casso... add unpack predicated unit test
2022-09-27 Luke Kenneth Casso... hack to check skipping on predicate being all-zero.
2022-09-27 Luke Kenneth Casso... sort out predicate loop-skip on pack/unpack
2022-09-27 Luke Kenneth Casso... adapt loops to include predicate-mask skipping in ISACaller
2022-09-27 Jacob Lifshayadd WIP jpeg decoder demo
2022-09-26 Jacob Lifshayadd more tests and fix missing corner case
2022-09-26 Jacob Lifshaypcdec.: change CR0.eq to be early-stop-needed to fit...
2022-09-26 Jacob Lifshayadd checks for pcdec. once=1
2022-09-26 Jacob Lifshaymore cleanup after swapping RA/RB for pcdec.
2022-09-26 Jacob Lifshayclean up after lkcl swapped RA/RB for pcdec.
2022-09-26 Luke Kenneth Casso... skipping on maskedout elements de-restricted when subst...
2022-09-26 Luke Kenneth Casso... add first predicate-mask test of pack/unpack
2022-09-26 Luke Kenneth Casso... get pack/unpack tests to use sv.ori to copy sequence...
2022-09-26 Luke Kenneth Casso... finally got pack/unpack working
2022-09-26 Luke Kenneth Casso... code-morph on loop-end detection in ISACaller
2022-09-26 Luke Kenneth Casso... explicit test of src/dststep end-condition in ISACaller...
2022-09-26 Luke Kenneth Casso... swap RA/RB so that RA|0 is used not RB|0
2022-09-25 Konstantinos Marga... comment out debug dumps
2022-09-25 Dmitry Selyutintest_pysvp64dis: sort ld/st idx stride specs
2022-09-25 Dmitry Selyutinpower_insn: always provide els for ld/st idx stride
2022-09-25 Dmitry Selyutinpysvp64asm: fix VLi attribute access
2022-09-25 Dmitry Selyutinpower_insn: fix and unify /vli specifier
2022-09-25 Luke Kenneth Casso... have to sanity-check dz/zz after full qualifier-process...
2022-09-25 Luke Kenneth Casso... add dz/sz assertion in is_bc mode
2022-09-25 Luke Kenneth Casso... whitespace
2022-09-24 Luke Kenneth Casso... move sea check to after all qualifiers are checked
2022-09-24 Luke Kenneth Casso... check variable rather than explicit == LDST_IDX
2022-09-24 Luke Kenneth Casso... add elstrided/sea on ldst_idx mode
2022-09-24 Dmitry Selyutintest_pysvp64dis: test ld/st idx SEA (simple)
2022-09-24 Dmitry Selyutinpower_insn: support SEA specifier
2022-09-24 Dmitry Selyutinpysvp64asm: support /sea specifier
2022-09-24 Dmitry Selyutinconsts: introduce SEA field
2022-09-24 Dmitry Selyutinpysvp64asm: fix comment layout
2022-09-24 Luke Kenneth Casso... set sv_mode to 0b01 in element-strided
2022-09-24 Luke Kenneth Casso... frickin frick
2022-09-24 Luke Kenneth Casso... add assert to stop failfirst+sea
2022-09-24 Luke Kenneth Casso... add extra RC1 test, without VLI.
2022-09-24 Luke Kenneth Casso... add RC1 support to ISACaller.
2022-09-24 Dmitry Selyutinpower_insn: slightly change table checking style
2022-09-24 Luke Kenneth Casso... add extra test_pysvp64dis.py test for ff=~RC1/vli mode
2022-09-24 Luke Kenneth Casso... whoops got mask/match test wrong in power_insn.py
2022-09-24 Luke Kenneth Casso... comment inv,CRbit swap in decode_bo
2022-09-24 Dmitry Selyutinsv_binutils: support RS opindex
2022-09-24 Dmitry Selyutinpower_insn: reorder mode tables to match the spec
2022-09-24 Dmitry Selyutinpower_insn: rename smr to mr
2022-09-24 Dmitry Selyutinsv_binutils: provide Boolean class and Rc field
2022-09-24 Dmitry Selyutinpower_insn: provide Record.Rc field
2022-09-24 Dmitry Selyutinpower_insn: simplify rsvd naming; drop unused rsvd
2022-09-24 Dmitry Selyutinpower_insn: replace Record.function with Record.mode
2022-09-24 Dmitry Selyutinpysvp64asm: expand vector register macros
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