2021-12-08 |
Luke Kenneth Casso... | add OP_FETCH_FAILED to MMU Function Unit |
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2021-12-08 |
Luke Kenneth Casso... | make LoadStore1 intsr_fault a "captured flag" - strictl... |
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2021-12-08 |
Luke Kenneth Casso... | remove MSR and add CIA to MMU Input Record |
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2021-12-08 |
Luke Kenneth Casso... | add instr_fault to LoadStore1 FSM |
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2021-12-08 |
Luke Kenneth Casso... | add new PortInterfaceBase external_busy() option |
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2021-12-08 |
Jacob Lifshay | add comment about draft instructions |
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2021-12-08 |
Jacob Lifshay | account for Mock absurdities |
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2021-12-07 |
Luke Kenneth Casso... | complete the i-cache fetch through the MMU, including... |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | set separate "iside" signal in LoadStore1 to not confuse it |
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2021-12-07 |
Luke Kenneth Casso... | start extending icache loadstore test |
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2021-12-07 |
Luke Kenneth Casso... | whoops another serious error in the CacheTagArray |
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2021-12-07 |
Luke Kenneth Casso... | add first i-cache fetch (non-virtual), no MMU lookup... |
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2021-12-07 |
Luke Kenneth Casso... | code-comments |
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2021-12-07 |
Luke Kenneth Casso... | add in I-Cache into LoadStore1 - presently unused ... |
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2021-12-07 |
Luke Kenneth Casso... | add discussion links and bugreport |
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2021-12-07 |
Luke Kenneth Casso... | invert mmureq statements |
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2021-12-07 |
Luke Kenneth Casso... | submodule tidyup |
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2021-12-07 |
Jacob Lifshay | make bitmanip operations conditional on pspec.draft_bit... |
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2021-12-07 |
Jacob Lifshay | format code |
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2021-12-07 |
Jacob Lifshay | move rotator mode assignments as requested by lkcl |
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2021-12-07 |
Jacob Lifshay | format code |
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2021-12-07 |
Luke Kenneth Casso... | tidyup, comments |
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2021-12-07 |
Luke Kenneth Casso... | debug print |
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2021-12-06 |
Luke Kenneth Casso... | another major bug, CacheTagArray valid was only 1 bit... |
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2021-12-06 |
Luke Kenneth Casso... | tidyup: move hit_set to DCachePendingHit in dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | dcache.py tidyup |
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2021-12-06 |
Luke Kenneth Casso... | rename dtlb to dtlb_valid and tidyup |
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2021-12-06 |
Luke Kenneth Casso... | convert TLBArray to TLBValidArray |
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2021-12-06 |
Luke Kenneth Casso... | convert DTLBUpdate to use a pair of Memorys |
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2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | update DTLBUpdate to reflect internal API now |
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2021-12-06 |
Luke Kenneth Casso... | ooo nasty bug. used tlb_hit.way instead of tlb_hit... |
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2021-12-06 |
Luke Kenneth Casso... | move DTLB Tags/Valids/PTEs into DTLBUpdate module |
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2021-12-06 |
Luke Kenneth Casso... | start moving TLBArray into DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | PLRUs were selecting an output index, only one selected |
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2021-12-06 |
Luke Kenneth Casso... | repeated copies of read/write addr/sel to Cache SRAMs |
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2021-12-06 |
Luke Kenneth Casso... | move bank of PLRUs to their own submodule in both dcach... |
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2021-12-06 |
Luke Kenneth Casso... | code-comments |
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2021-12-06 |
Luke Kenneth Casso... | use binary-to-unary encoders in dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | global (one) do_read signal in cache_rams dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | use one-hot binary-to-unary in dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | use i_in.req to gate hit_way via Decoder in icache.py |
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2021-12-06 |
Luke Kenneth Casso... | use Decoder (binary-to-unary) in icache.py to deal... |
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2021-12-05 |
Luke Kenneth Casso... | use unary encoding (one-hot) for replace_way hit_way... |
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2021-12-05 |
Luke Kenneth Casso... | code-comments |
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2021-12-05 |
Luke Kenneth Casso... | whitespace and minor cleanup of D-Cache |
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2021-12-05 |
Luke Kenneth Casso... | more use of TLBHit Record in D-Cache |
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2021-12-05 |
Luke Kenneth Casso... | correct tlb_hit_way and index sizes, use TLBHit Record... |
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2021-12-05 |
Luke Kenneth Casso... | use TLBRecord in D-Cache for which TLB is selected |
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2021-12-05 |
Luke Kenneth Casso... | split out TLBRecord, correct number of valid bits |
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2021-12-05 |
Luke Kenneth Casso... | use Record in DCache for TLB |
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2021-12-05 |
Luke Kenneth Casso... | use Record in D-Cache Cache Tags |
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2021-12-05 |
Luke Kenneth Casso... | whitespace |
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2021-12-05 |
Luke Kenneth Casso... | use Record for I-Cache Cache Tag/Valid |
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2021-12-05 |
Luke Kenneth Casso... | whitespace |
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2021-12-05 |
Luke Kenneth Casso... | use Record for ICache TLB |
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2021-12-05 |
Luke Kenneth Casso... | sorting out test_mmu_dcache.py to use wb_get |
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2021-12-05 |
Luke Kenneth Casso... | convert icache.py to standard wishbone Interface |
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2021-12-05 |
Luke Kenneth Casso... | fake up wishbone stall signal in icache. |
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2021-12-05 |
Luke Kenneth Casso... | fix icache row store issue |
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2021-12-05 |
Luke Kenneth Casso... | using same tag/row functions as in dcache.py |
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2021-12-05 |
Luke Kenneth Casso... | more signal sizes in icache.py |
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2021-12-05 |
Luke Kenneth Casso... | incorrect Signal sizes in icache.py, |
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2021-12-05 |
Luke Kenneth Casso... | sorting out icache.py, used to work |
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2021-12-05 |
Luke Kenneth Casso... | remove redundant code |
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2021-12-05 |
Luke Kenneth Casso... | add I-Cache standard bus (not used yet) |
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2021-12-05 |
Luke Kenneth Casso... | remove yet another duplicate copy of wb_get, possible... |
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2021-12-05 |
Luke Kenneth Casso... | replace yet another duplicate copy of wb_get, possible... |
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2021-12-05 |
Luke Kenneth Casso... | wishbone bus convert on dcache |
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2021-12-05 |
Luke Kenneth Casso... | correct import of wg_get function |
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2021-12-04 |
Luke Kenneth Casso... | remove yet another duplicated copy of wb_get and add... |
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2021-12-04 |
Luke Kenneth Casso... | rename function which needs replacing |
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2021-12-04 |
Luke Kenneth Casso... | should have been using common version of wb_get, not... |
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2021-12-04 |
Luke Kenneth Casso... | should not have been duplicating wb_get function in... |
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2021-12-04 |
Luke Kenneth Casso... | get test_mmu_dcache.py working again |
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2021-12-04 |
Luke Kenneth Casso... | remove wb_get, should not have been duplicated |
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2021-12-04 |
Luke Kenneth Casso... | remove wb_get, should not have been massively duplicate... |
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2021-12-04 |
Luke Kenneth Casso... | fix return results from pi_ld |
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2021-12-04 |
Luke Kenneth Casso... | wark-wark, broke mmu with removing rin. reverted |
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2021-12-04 |
Tobias Platen | fixed wait_addr to exit immediately on exception |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | tidyup, comments |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | tidyup mmu |
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2021-12-04 |
Luke Kenneth Casso... | sigh in MMU FSM use direct access to ldst.dar/dsisr... |
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2021-12-04 |
Luke Kenneth Casso... | remove DAR from PortInterface (where is the data going... |
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2021-12-04 |
Luke Kenneth Casso... | stop using dar_o from PortInterface, get DAR directly... |
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2021-12-04 |
Luke Kenneth Casso... | put DSISR and DAR publicly accessible in LoadStore1 |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | whoops fix up exception happened if alignment triggers... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | fix pi_st which should not be trying to wait for the... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | fixing DAR updating from exceptions |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | whoops |
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2021-12-04 |
Luke Kenneth Casso... | MMU lookup DSISR load bit inverted in LoadStore1 |
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2021-12-04 |
Luke Kenneth Casso... | store DAR in LoadStore1 |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | not busy if excrption occurs on MMU_LOOKUP in loadstore.py |
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2021-12-04 |
Luke Kenneth Casso... | add means to update dsisr from MMU FSM. TODO: add a... |
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2021-12-03 |
Luke Kenneth Casso... | priv_mode/virt_mode are set in the request, which is... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | in loadstore.py set align_intr from request which comes... |
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2021-12-03 |
Luke Kenneth Casso... | driver conflict on priv_mode and virt_mode, do not... |
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2021-12-03 |
Luke Kenneth Casso... | fix up test_loadstore1.py |
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2021-12-03 |
Luke Kenneth Casso... | in loadstore.py, when an exception is done or if the FSM |
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