2020-10-08 |
Cole Poirier | remove singleton dict per https://bugs.libre-soc.org... |
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2020-10-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-10-08 |
Tobias Platen | add WIP test_pipe_caller.py for mmu |
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2020-10-08 |
Luke Kenneth Casso... | add incoming PortInterface to be connected to LoadStore... |
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2020-10-08 |
Luke Kenneth Casso... | JTAG boundary scan test 1st attempt |
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2020-10-08 |
Luke Kenneth Casso... | rework jtag test to use JTAG class not DMITAP |
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2020-10-08 |
Luke Kenneth Casso... | split out jtag util functions to separate module |
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2020-10-08 |
Cole Poirier | first attempt at 3) of |
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2020-10-08 |
Cole Poirier | modify wb_get per 1) of https://bugs.libre-soc.org... |
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2020-10-07 |
Tobias Platen | connect mmu_done, ldst_error, cache_paradox |
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2020-10-07 |
Luke Kenneth Casso... | missing invert_in field from shiftrot input record |
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2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
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2020-10-07 |
Jacob Lifshay | fix div tests |
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2020-10-07 |
Jacob Lifshay | Fix forgotten test_pipe_caller changes from e0b4334c7d8... |
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2020-10-06 |
Tobias Platen | remove redunant signals |
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2020-10-06 |
Luke Kenneth Casso... | update comments on pimem.py |
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2020-10-06 |
Tobias Platen | test_mmu_dcache_pi.py |
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2020-10-06 |
Luke Kenneth Casso... | comments |
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2020-10-06 |
Luke Kenneth Casso... | add ports function to DummyPLL |
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2020-10-06 |
Luke Kenneth Casso... | use pdecode2.do not pdecode2.e in test_pipe_caller... |
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2020-10-06 |
Luke Kenneth Casso... | skip Decode2ToOperand from PowerDecodeSubset |
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2020-10-06 |
Luke Kenneth Casso... | comment SRR1 mem.exception |
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2020-10-06 |
Luke Kenneth Casso... | add SRR1 setting for LDST memory exception trap |
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2020-10-06 |
Luke Kenneth Casso... | passing LDSTException over to Trap Pipeline |
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2020-10-06 |
Luke Kenneth Casso... | add LDSTException decode/handling in PowerDecoder2 |
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2020-10-06 |
Luke Kenneth Casso... | make LDSTException fields added from list of fieldnames |
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2020-10-06 |
Luke Kenneth Casso... | move LDSTException to mem_types |
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2020-10-06 |
Luke Kenneth Casso... | add LDSTException to PortInterface |
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2020-10-06 |
Luke Kenneth Casso... | add sdr bypass routing via JTAG boundary scan |
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2020-10-06 |
Jacob Lifshay | add divde regression test |
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2020-10-06 |
Jacob Lifshay | add moduw regression test |
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2020-10-06 |
Jacob Lifshay | add workaround for nmigen bug #502 |
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2020-10-06 |
Jacob Lifshay | add modsw regression |
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2020-10-06 |
Jacob Lifshay | add test case for divweu regression |
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2020-10-06 |
Jacob Lifshay | print regs in hex |
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2020-10-05 |
Luke Kenneth Casso... | add debug / investigation print statements |
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2020-10-05 |
Jacob Lifshay | `deepcopy` from cache instead of recreating parsers... |
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2020-10-05 |
Jacob Lifshay | format code |
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2020-10-05 |
Cole Poirier | icache.py fix ispow2() util fn per https://bugs.libre... |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | return test rather than "if test return True else False" |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Cole Poirier | icache.py add python asserts that were a TODO commented... |
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2020-10-05 |
Cole Poirier | icache.py fix formatting, mostly due to reduced indenta... |
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2020-10-05 |
Cole Poirier | icache.py remove comment that contained the entirety... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss WAIT_ACK FSM state into... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss CLR_TAG FSM state into metho... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss IDLE FSM state into method... |
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2020-10-05 |
Jacob Lifshay | simplify create_args |
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2020-10-05 |
Jacob Lifshay | Sort returned variables to make sure `overflow` is... |
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2020-10-05 |
Jacob Lifshay | format caller.py |
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2020-10-04 |
Jacob Lifshay | change div FSM pipeline unit to not have a combinatoria... |
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2020-10-04 |
Luke Kenneth Casso... | significant reorg of the litex pinspecs to use pinmux... |
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2020-10-04 |
Luke Kenneth Casso... | submodule update |
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2020-10-04 |
Luke Kenneth Casso... | remove ls180io import |
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2020-10-04 |
Luke Kenneth Casso... | move ls180io.py back into ls180.py |
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2020-10-03 |
Luke Kenneth Casso... | allow i2c to be routed via JTAG |
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2020-10-03 |
Luke Kenneth Casso... | nope. put it back and connect to platform pads in... |
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2020-10-03 |
Luke Kenneth Casso... | move iopad litex creation to ls180soc.py |
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2020-10-03 |
Luke Kenneth Casso... | minor reorg on JTAG, allow alternative pinset dict... |
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2020-10-03 |
Jacob Lifshay | add regression testcase |
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2020-10-02 |
Cole Poirier | icache.py add req_hit_way as arg to icache_comb, actual... |
tree | commitdiff |
2020-10-01 |
Cole Poirier | icache.py add missing comb signal assignments per https... |
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2020-10-01 |
Luke Kenneth Casso... | arg CacheRam read output needs delay by 1 cycle |
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2020-10-01 |
Luke Kenneth Casso... | do not pass cache row array around, just the current row |
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2020-10-01 |
Luke Kenneth Casso... | revert bug in icache wishbone ack |
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2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
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2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
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2020-10-01 |
Cesar Strauss | Add GTKWave document to test_compunit_fsm |
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2020-09-30 |
Luke Kenneth Casso... | add I2C into ls180 |
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2020-09-30 |
Luke Kenneth Casso... | add ASIC version of I2C Master |
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2020-09-30 |
Luke Kenneth Casso... | clean up row store and wb adr in icache |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | hmm only set wishbone address if ack is actually received |
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2020-09-30 |
Luke Kenneth Casso... | add more debug prints in icache |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | remove more reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | remove reviewed comments |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | comb on wr_index not sync |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | start removing reviewed comments |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | use same constant name (confusing otherwise) |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | need asserts |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | halve the number of icache lines for now |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | use Repl rather than for-loop to copy bit |
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2020-09-30 |
Luke Kenneth Casso... | move loop invariant test out of loop |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | reduce size of ilang file by a factor of FIVE |
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2020-09-30 |
Luke Kenneth Casso... | store tag in temp signal |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | reduce gate usage by getting cache row only not entire... |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | fix read_tag to use word_select correctly |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | forgot to add PLRUs as submodules |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix combinatorial loop with by testing temp... |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix is_last_row_addr, get_next_row_addr |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py trying to sort out test failure, added r... |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix rarange |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
tree | commitdiff |
2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | reduce not-connected IO pins |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | missing pspec |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | connect SDRAM dqm to wrdata_mask |
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