something weird going on with div. interaction between tests
[soc.git] / src /
2020-07-09 Luke Kenneth Casso... something weird going on with div. interaction between...
2020-07-09 Luke Kenneth Casso... simplify setting of mul overflow into xer_ov
2020-07-09 Luke Kenneth Casso... clarifying comments on setting xer_ov/so
2020-07-09 Luke Kenneth Casso... DIV overflow needs to be copied into both bits of XER.ov
2020-07-09 Luke Kenneth Casso... add debug output of DIV results
2020-07-09 Luke Kenneth Casso... check result first then CR second
2020-07-09 Luke Kenneth Casso... munge alu_fsm Shifter into looking like CompALU API...
2020-07-09 Luke Kenneth Casso... resolving issues with div tests (turned out to be nmuti...
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-09 Cesar StraussDefine ports for a simple sequential Shifter
2020-07-09 Luke Kenneth Casso... irony comment on how one line creates a massive array...
2020-07-09 Luke Kenneth Casso... add new stages etc. to get multiply working without...
2020-07-09 Luke Kenneth Casso... create new DivMulOutputData which does not have CA...
2020-07-09 Luke Kenneth Casso... make carry output handling optional in common output...
2020-07-09 Luke Kenneth Casso... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... sorting out setting of XER
2020-07-08 Luke Kenneth Casso... add spr to fast reg converter
2020-07-08 Luke Kenneth Casso... got test_issuer operational on one unit test
2020-07-08 Luke Kenneth Casso... switch assembler to little-endian
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking...
2020-07-08 Luke Kenneth Casso... add test trap simulator unit test
2020-07-08 Luke Kenneth Casso... allow qemu to stop at specified end point
2020-07-08 Luke Kenneth Casso... add mtspr and bcctrl instructions to helloworld test
2020-07-08 Luke Kenneth Casso... add option to qemu to break at known alternate address
2020-07-08 Luke Kenneth Casso... add to/from spr test (mtspr, mfspr)
2020-07-08 Luke Kenneth Casso... add code-fragment from microwatt helloworld
2020-07-08 Luke Kenneth Casso... add a simple addis test (regression)
2020-07-08 Luke Kenneth Casso... copy binary loaded from disk into data memory as well
2020-07-08 Cesar StraussStart the FSM-based ALU example.
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add hello world binary test
2020-07-07 Luke Kenneth Casso... whoops error in test of dynamic parameter
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Cesar StraussClear input data along with valid_i
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth Casso... whoops got Function.NONE test wrong in PowerDecode2
2020-07-07 Luke Kenneth Casso... remove unneeded record field from logical_input_record
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN)
2020-07-07 Luke Kenneth Casso... update opcode map for OP_ATTN
2020-07-07 Luke Kenneth Casso... add halted condition in ISACaller, when attn instructio...
2020-07-07 Luke Kenneth Casso... debugging termination / OP_ATTN
2020-07-07 Luke Kenneth Casso... add ATTN unit test
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py
2020-07-06 Luke Kenneth Casso... use ComMULOpSubset in mul pipeline
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... add mul unit to test_issuer
2020-07-06 Luke Kenneth Casso... add mul compunit
2020-07-06 Luke Kenneth Casso... whoops forgot that the mul pipeline is actually a pipel...
2020-07-06 Luke Kenneth Casso... do abs slightly differently in SelectableInt
2020-07-06 Luke Kenneth Casso... continue mul unit test debugging
2020-07-06 Luke Kenneth Casso... add MULS (signed) version of multiply
2020-07-06 Luke Kenneth Casso... improve debug for test_sim.py
2020-07-06 Luke Kenneth Casso... add mullw test to qemu sim
2020-07-06 Luke Kenneth Casso... fix SelectableInt abs
2020-07-06 Luke Kenneth Casso... add first simulator mul test
2020-07-06 Luke Kenneth Casso... investigating mul pipeline
2020-07-06 Luke Kenneth Casso... SelectableInt: make __mul__ return enough space to...
2020-07-06 Luke Kenneth Casso... first cut at mul test pipeline
2020-07-06 Luke Kenneth Casso... add first cut at fu mul pipeline
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-06 Luke Kenneth Casso... adding OP_MTMSR test
2020-07-06 Luke Kenneth Casso... add mtmsr internal op
2020-07-06 Luke Kenneth Casso... add mtmsr internal op
2020-07-06 Luke Kenneth Casso... sort out initialisation of TstL0CacheBuffer in ldst...
2020-07-06 Cesar StraussAssert n.ready_i at the beginning of the cycle
2020-07-06 Cesar StraussRemove wait state to demonstrate zero-delay reception.
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussFinally add some well needed comments
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussAdd some wait states in each process
2020-07-06 Cesar StraussNegate inputs after use
2020-07-06 Cesar StraussAdd other tests
2020-07-06 Cesar StraussImplement receiver
2020-07-06 Cesar StraussImplement sender.
2020-07-06 Cesar StraussBegin a new parallel test
2020-07-05 Luke Kenneth Casso... add mtmsr tests (fail)
2020-07-05 Luke Kenneth Casso... check trap compunit output properly
2020-07-05 Luke Kenneth Casso... check msr in trap test, fix OP_RFID
2020-07-05 Luke Kenneth Casso... add an illegal instruction trap test
2020-07-05 Luke Kenneth Casso... set up a trap function for microcode override
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... stop debug output in power_decoder
2020-07-05 Luke Kenneth Casso... comments in power_regspec_map.py
2020-07-05 Luke Kenneth Casso... comment on spr2, not needed
2020-07-05 Luke Kenneth Casso... check xer_out not xer_in
2020-07-05 Luke Kenneth Casso... split out Decode2ToExecuteType fields involving registers
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... check spr1 in test spr compunit
2020-07-05 Luke Kenneth Casso... get/set slow spr in spr test_pipe_caller
2020-07-05 Luke Kenneth Casso... add first spr compunit test (not working yet)
2020-07-05 Luke Kenneth Casso... add SPR test case, commented out for now
2020-07-05 Luke Kenneth Casso... move valid signal out of Decode2ToExecute1Type and...
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