Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 14:05:05 +0000 (15:05 +0100)]
move regspec / rdflag decoding functions out of PowerDecode2
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 13:57:54 +0000 (14:57 +0100)]
sort out instruction stop/cancel when adding a new issuer FSM state
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 11:59:01 +0000 (12:59 +0100)]
put multi-ports back (for read) on int and fast regfiles
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 11:10:06 +0000 (12:10 +0100)]
reduce decoder pathways when exception occurs
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:26:00 +0000 (00:26 +0100)]
divide shiftrot pipeline into 2 (simple last)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:25:36 +0000 (00:25 +0100)]
divide alu pipeline into 2 (simple last)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:19:34 +0000 (00:19 +0100)]
divide logical pipe into 2 (simple phase last)
Jacob Lifshay [Fri, 14 Aug 2020 04:22:01 +0000 (21:22 -0700)]
running the simulator works!
Jacob Lifshay [Thu, 13 Aug 2020 23:18:03 +0000 (16:18 -0700)]
add --cpu=libresoc to Makefile
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:44:29 +0000 (22:44 +0100)]
fix dmi reg read
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:23:18 +0000 (22:23 +0100)]
code-shuffle
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:23:08 +0000 (22:23 +0100)]
remove use of latchregigister, replace with sync on rd.go_i
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 20:33:25 +0000 (21:33 +0100)]
sync on pc writing when changed
Cole Poirier [Thu, 13 Aug 2020 19:05:10 +0000 (12:05 -0700)]
dcache.py add initial imports
Cole Poirier [Thu, 13 Aug 2020 19:01:11 +0000 (12:01 -0700)]
mem_types.py add more types from common.vhdl
Cole Poirier [Thu, 13 Aug 2020 18:45:25 +0000 (11:45 -0700)]
move memory related types from mmu.py into new file mem_types.py as they
are used by icache and dcache as well
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 17:42:12 +0000 (18:42 +0100)]
sync on reset in compalu
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 16:52:33 +0000 (17:52 +0100)]
add forwarding-bus mode to Regfile Memory (and disable it)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 15:49:35 +0000 (16:49 +0100)]
sync on port interface address in ld/st compunit, and use sync on oper_i
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 15:49:07 +0000 (16:49 +0100)]
another sync to cut latency
Cole Poirier [Thu, 13 Aug 2020 15:30:27 +0000 (08:30 -0700)]
Initial commit of translation of microwatt dcache.vhdl into nmigen
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 14:46:58 +0000 (15:46 +0100)]
remove latchregister, sync src oper_i into MultiCompUnit
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 14:23:34 +0000 (15:23 +0100)]
minor tidyup on alu compunit:
* sync on oper_r because there is time to wait for src reads
* get immediates from op not oper_r
* use rising_edge rather than manual pulse creation
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 12:59:48 +0000 (13:59 +0100)]
plenty of time to wait for operand, so use "sync" in MultiCompUnit
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 12:34:36 +0000 (13:34 +0100)]
sigh. convert Fast regfile to binary
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 11:45:52 +0000 (12:45 +0100)]
sync on read of regfile ports
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 11:25:32 +0000 (12:25 +0100)]
sigh. convert INT regfile to binary addressing
Luke Kenneth Casson Leighton [Wed, 12 Aug 2020 15:50:03 +0000 (16:50 +0100)]
create a RegFileMem class that uses Memory
Jacob Lifshay [Wed, 12 Aug 2020 21:23:58 +0000 (14:23 -0700)]
add run_sim to Makefile
Cole Poirier [Wed, 12 Aug 2020 18:55:20 +0000 (11:55 -0700)]
mmu.py add skeleton sim and test functions from regfile/regfile.py
Cole Poirier [Wed, 12 Aug 2020 18:53:51 +0000 (11:53 -0700)]
Delete unnecessary mmu dir, move mmu.py out of mmu dir back to
experiment dir
Cole Poirier [Wed, 12 Aug 2020 18:52:05 +0000 (11:52 -0700)]
Revert "Remove mmu dir and associated mmu/test/ dir" because I forgot to
add mmu.py to the commit, so it shows deleted instead of renamed/moved
This reverts commit
e97b5223a871498a9dd434103b2ecd4a13c06440.
Cole Poirier [Wed, 12 Aug 2020 18:45:20 +0000 (11:45 -0700)]
Remove mmu dir and associated mmu/test/ dir
Cole Poirier [Wed, 12 Aug 2020 18:37:13 +0000 (11:37 -0700)]
Remove rst signals, fix len of hex Consts, fix variable assignment values that didn't match mmu.vhdl, fix all vhdl '&' to Cat()'s', fix formatting
Cole Poirier [Wed, 12 Aug 2020 18:34:42 +0000 (11:34 -0700)]
Create dir experiment/mmu then mmu/test with skeleton test
infrastructure copied from fu/mul/test
Cole Poirier [Wed, 12 Aug 2020 17:55:14 +0000 (10:55 -0700)]
mmu.py add RecordObject classes from common.vhdl input types https://bugs.libre-soc.org/show_bug.cgi?id=450#c31
Cole Poirier [Wed, 12 Aug 2020 17:02:42 +0000 (10:02 -0700)]
mmu.py remove TODOs for vhdl (others => '0') as they are irrelevant in
nmigen
Cole Poirier [Wed, 12 Aug 2020 16:51:16 +0000 (09:51 -0700)]
mmu.py fix or(block of logic) to be (block of logic).bool() https://bugs.libre-soc.org/show_bug.cgi?id=450#c31
Cole Poirier [Wed, 12 Aug 2020 16:47:09 +0000 (09:47 -0700)]
mmu.py fix length of hex const https://bugs.libre-soc.org/show_bug.cgi?id=450#c31
Cole Poirier [Wed, 12 Aug 2020 16:45:15 +0000 (09:45 -0700)]
mmu.py remove class AddrShifter
Cole Poirier [Wed, 12 Aug 2020 00:10:56 +0000 (17:10 -0700)]
Fix typo in mmu.py
Cole Poirier [Tue, 11 Aug 2020 21:48:53 +0000 (14:48 -0700)]
mmu.py fix formatting, use Cat() where '&' in mmu.vhdl
Tobias Platen [Tue, 11 Aug 2020 17:16:47 +0000 (19:16 +0200)]
initial version of L0CacheBuffer2
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 14:22:08 +0000 (15:22 +0100)]
sigh, remove yet another int regfile read port
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 14:05:27 +0000 (15:05 +0100)]
massive reduction in gate count by using alternative read/write port mux
using Mux followed by or tree-reduce, the large number of read/write
port selection(s) creates a more efficient bus
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 13:37:51 +0000 (14:37 +0100)]
reduce regfile port usage for INT and FAST
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 13:32:25 +0000 (14:32 +0100)]
prepare write ports to be shared
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 13:24:50 +0000 (14:24 +0100)]
move write regfile picker creation to new function
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 13:13:13 +0000 (14:13 +0100)]
reduce regfile ports by creating separate STATE regfile
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 12:17:18 +0000 (13:17 +0100)]
whoops fix change of variable (state) msr/pc
Luke Kenneth Casson Leighton [Tue, 11 Aug 2020 12:07:22 +0000 (13:07 +0100)]
reducing regfile port usage by sharing read ports
gets gate count down considerably
Samuel A. Falvo II [Mon, 10 Aug 2020 21:17:08 +0000 (14:17 -0700)]
WIP!! Make MUL pipeline proof run again.
Removed existing set of tests, as they didn't seem to be relevant
(appeared to be copy-and-paste template code). Next steps is to go
through main_stage.py and implement corresponding proofs.
Cole Poirier [Mon, 10 Aug 2020 17:45:49 +0000 (10:45 -0700)]
Fix typo in mmu.py
Cole Poirier [Mon, 10 Aug 2020 17:42:21 +0000 (10:42 -0700)]
Fix typo mmu.py
Cole Poirier [Mon, 10 Aug 2020 16:26:46 +0000 (09:26 -0700)]
Global search and replace (^, |), fixes bug 450 comment 11, fix
formatting
Cole Poirier [Mon, 10 Aug 2020 16:17:36 +0000 (09:17 -0700)]
fix bug 450 comments 8,9,10
Cole Poirier [Mon, 10 Aug 2020 16:10:51 +0000 (09:10 -0700)]
Fix bug 450 comment 7
Cole Poirier [Mon, 10 Aug 2020 16:05:53 +0000 (09:05 -0700)]
mmu.py add line I forgot to translate from mmu.vhdl
Cole Poirier [Mon, 10 Aug 2020 01:50:40 +0000 (18:50 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Mon, 10 Aug 2020 01:50:08 +0000 (18:50 -0700)]
mmu.vhdl translation to mmu.py 95 percent complete
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:33:50 +0000 (22:33 +0100)]
stop combinatorial loop in pi2ls
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:25:32 +0000 (22:25 +0100)]
write pulse in issuer
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:18:16 +0000 (22:18 +0100)]
fix combinatorial loop in ldst compunit
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 18:47:27 +0000 (19:47 +0100)]
use rising edge detection on st go_i/rel_o
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:43:48 +0000 (16:43 +0100)]
add logical test issuer case
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:25:24 +0000 (16:25 +0100)]
get rid of MSR read combinatorial loop
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:08:58 +0000 (16:08 +0100)]
delay go_st by one cycle, break combinatorial loop
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 14:20:11 +0000 (15:20 +0100)]
divwo case makes test_issuer stay busy!
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 14:01:23 +0000 (15:01 +0100)]
add extra divwo regression test
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 09:57:58 +0000 (10:57 +0100)]
compalu combinatorial loop detected
Cole Poirier [Sat, 8 Aug 2020 17:58:00 +0000 (10:58 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sat, 8 Aug 2020 17:57:37 +0000 (10:57 -0700)]
Update test case_mulli
Tobias Platen [Sat, 8 Aug 2020 11:54:42 +0000 (13:54 +0200)]
addr_split.py: shift bytes not bits
Cole Poirier [Fri, 7 Aug 2020 23:50:24 +0000 (16:50 -0700)]
Update test case_mulli
Cole Poirier [Fri, 7 Aug 2020 01:05:10 +0000 (18:05 -0700)]
Update test case_mulli, I think it now works correctly
Cole Poirier [Fri, 7 Aug 2020 00:19:49 +0000 (17:19 -0700)]
Update mulli to try to use immediates not registers
Cole Poirier [Thu, 6 Aug 2020 19:21:09 +0000 (12:21 -0700)]
Fix mmu.py formatting
Cole Poirier [Thu, 6 Aug 2020 18:18:20 +0000 (11:18 -0700)]
Fix formatting
Cole Poirier [Thu, 6 Aug 2020 17:53:26 +0000 (10:53 -0700)]
Initial commit of translation of microwatt mmu.vhdl into nmigen
Cole Poirier [Thu, 6 Aug 2020 17:49:56 +0000 (10:49 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Thu, 6 Aug 2020 17:49:30 +0000 (10:49 -0700)]
Update test case_all_rb_close_to_ov
Cole Poirier [Thu, 6 Aug 2020 17:28:48 +0000 (10:28 -0700)]
Update test case_all_rb_close_to_ov
Luke Kenneth Casson Leighton [Thu, 6 Aug 2020 15:38:47 +0000 (16:38 +0100)]
fix LDST PortInterface FSM interaction
when the WB Bus delayed "ack", the LDST PI FSM was not "listening" and
assumed that the operation had completed. a bit of a rewrite was required
to get it to wait until LD/ST operations had actually fully completed
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:46:51 +0000 (19:46 +0100)]
MULS on parameter b needed to check whether it was sign-extended
Cole Poirier [Thu, 6 Aug 2020 00:38:33 +0000 (17:38 -0700)]
Add special test for case_mulli, apply autopep8
Cole Poirier [Wed, 5 Aug 2020 21:58:07 +0000 (14:58 -0700)]
Add test case_all_rb_close_to_ov
Cole Poirier [Wed, 5 Aug 2020 21:21:19 +0000 (14:21 -0700)]
Remove mulli from instrs in test case_all*, add TODO for mulli special
test case
Cole Poirier [Wed, 5 Aug 2020 21:02:47 +0000 (14:02 -0700)]
Add new test_values to tests case_all and case_all_rb_randint
Cole Poirier [Wed, 5 Aug 2020 20:56:11 +0000 (13:56 -0700)]
Add second case_all test where rb is randint
Tobias Platen [Wed, 5 Aug 2020 18:45:45 +0000 (20:45 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 5 Aug 2020 18:45:40 +0000 (20:45 +0200)]
undo changes that fix unit test, but do not solve anything
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:19:58 +0000 (19:19 +0100)]
rename ibus/dbus (shorten)
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:13:06 +0000 (19:13 +0100)]
clear sel on loadstore
Tobias Platen [Wed, 5 Aug 2020 18:15:09 +0000 (20:15 +0200)]
fix LDSTSplitter
Cole Poirier [Wed, 5 Aug 2020 17:18:22 +0000 (10:18 -0700)]
Remove madd* isns, added madd* isns test TODO
Cole Poirier [Wed, 5 Aug 2020 16:56:09 +0000 (09:56 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 13:31:38 +0000 (14:31 +0100)]
adding bus data width of 64 in litex sim doesnt work
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 11:32:45 +0000 (12:32 +0100)]
add div test cases into test_issuer.py
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 09:29:44 +0000 (10:29 +0100)]
add div FSM as default for test_issuer in verilog and ilang gen
Cole Poirier [Wed, 5 Aug 2020 04:42:56 +0000 (21:42 -0700)]
Merge branch 'master' of git.libre-soc.org:soc