Michael Nolan [Tue, 26 May 2020 17:33:19 +0000 (13:33 -0400)]
Rewrite proof to be more in line with what appears in the wiki
Luke Kenneth Casson Leighton [Tue, 26 May 2020 15:54:33 +0000 (16:54 +0100)]
sort-of (maybe) implemented a virtual port on top of RegFileArray.
needs checking
Luke Kenneth Casson Leighton [Tue, 26 May 2020 15:03:58 +0000 (16:03 +0100)]
try new variant of VirtualRegFile
Luke Kenneth Casson Leighton [Tue, 26 May 2020 12:45:58 +0000 (13:45 +0100)]
use nmutil treereduce
Luke Kenneth Casson Leighton [Tue, 26 May 2020 11:44:18 +0000 (12:44 +0100)]
continue virtual regfile port
Luke Kenneth Casson Leighton [Tue, 26 May 2020 11:43:57 +0000 (12:43 +0100)]
whitespace, add commentary
colepoirier [Tue, 26 May 2020 01:04:37 +0000 (18:04 -0700)]
First attempt at implementing block access rd and wr regfile port onto
an array-based regfile
Cesar Strauss [Mon, 25 May 2020 22:50:32 +0000 (19:50 -0300)]
Check that busy_o doesn't rise on its own
Cesar Strauss [Mon, 25 May 2020 22:28:43 +0000 (19:28 -0300)]
Implement the issue_i/busy_o protocol check.
It will timeout, until the rel/go signals are implemented.
Cesar Strauss [Mon, 25 May 2020 19:11:03 +0000 (16:11 -0300)]
Move process list to CompUnitParallelTest
The process list (implementation detail) is best left for the class.
Michael Nolan [Mon, 25 May 2020 19:11:32 +0000 (15:11 -0400)]
Correct polarity of shadow signal
Luke Kenneth Casson Leighton [Mon, 25 May 2020 19:00:45 +0000 (20:00 +0100)]
document shadown inversion
Michael Nolan [Mon, 25 May 2020 18:53:49 +0000 (14:53 -0400)]
Add link to compunit wiki page
Michael Nolan [Mon, 25 May 2020 18:47:58 +0000 (14:47 -0400)]
Correct property numbers, add assertions about busy
Luke Kenneth Casson Leighton [Mon, 25 May 2020 18:45:55 +0000 (19:45 +0100)]
update comments on compalu_multi.py
Michael Nolan [Mon, 25 May 2020 18:28:42 +0000 (14:28 -0400)]
Add assertions about go_wr and wr_rel
Michael Nolan [Mon, 25 May 2020 18:12:01 +0000 (14:12 -0400)]
Minor cleanup of comments
Michael Nolan [Mon, 25 May 2020 18:10:54 +0000 (14:10 -0400)]
Minor changes to alu_hier.py to allow it to be used in proof
Michael Nolan [Mon, 25 May 2020 18:08:20 +0000 (14:08 -0400)]
Begin working on proof for compunit/fu
Luke Kenneth Casson Leighton [Mon, 25 May 2020 15:28:30 +0000 (16:28 +0100)]
add some more stub comments
Luke Kenneth Casson Leighton [Mon, 25 May 2020 15:24:50 +0000 (16:24 +0100)]
yield blank so test passes
Luke Kenneth Casson Leighton [Mon, 25 May 2020 15:24:10 +0000 (16:24 +0100)]
add stubs
Luke Kenneth Casson Leighton [Mon, 25 May 2020 15:21:40 +0000 (16:21 +0100)]
add comments
Cesar Strauss [Mon, 25 May 2020 15:07:15 +0000 (12:07 -0300)]
Fix detection of busy_o inside the monitor process
Found the bug literally seconds after pushing...
Cesar Strauss [Mon, 25 May 2020 14:53:42 +0000 (11:53 -0300)]
Proof of concept of a parallel test
It doesn't work as expected.
For some reason, only the driver sees the rise of busy_o.
Tobias Platen [Mon, 25 May 2020 14:31:15 +0000 (16:31 +0200)]
fix own copy/paste error
Tobias Platen [Mon, 25 May 2020 14:29:39 +0000 (16:29 +0200)]
whitespace fix in docstring
Luke Kenneth Casson Leighton [Mon, 25 May 2020 14:24:31 +0000 (15:24 +0100)]
correct links in regfile docstring
Luke Kenneth Casson Leighton [Mon, 25 May 2020 14:13:16 +0000 (15:13 +0100)]
document regfiles
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:54:06 +0000 (14:54 +0100)]
argh! frickin MACos terminal expanded out to 86x30 not 80x30
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:52:40 +0000 (14:52 +0100)]
add docstring
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:43:15 +0000 (14:43 +0100)]
add INT, SPR and CR regfiles
Tobias Platen [Mon, 25 May 2020 13:41:49 +0000 (15:41 +0200)]
refactoring (see #216 Comment 43)
Tobias Platen [Mon, 25 May 2020 13:03:54 +0000 (15:03 +0200)]
whitespace changes
Luke Kenneth Casson Leighton [Mon, 25 May 2020 11:44:38 +0000 (12:44 +0100)]
quick addition of zero+immed test to LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 25 May 2020 10:43:28 +0000 (11:43 +0100)]
must not do rd-req checking when both imm and zero mode are enabled
Tobias Platen [Mon, 25 May 2020 09:47:00 +0000 (11:47 +0200)]
implement DataMerger interface
Luke Kenneth Casson Leighton [Mon, 25 May 2020 03:43:56 +0000 (04:43 +0100)]
add zero immed on LDST, untested
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:26:46 +0000 (03:26 +0100)]
comment out invalid test
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:23:10 +0000 (03:23 +0100)]
lots of greater than 80 chars
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:19:20 +0000 (03:19 +0100)]
switch out req rel if immediate enabled
Cesar Strauss [Mon, 25 May 2020 00:40:52 +0000 (21:40 -0300)]
Show oper_r and oper_i in the signal list, in simulation
Luke Kenneth Casson Leighton [Mon, 25 May 2020 00:11:49 +0000 (01:11 +0100)]
mention zeroing
Luke Kenneth Casson Leighton [Mon, 25 May 2020 00:09:54 +0000 (01:09 +0100)]
add links to pseudocode
Luke Kenneth Casson Leighton [Sun, 24 May 2020 23:58:19 +0000 (00:58 +0100)]
spelling
Luke Kenneth Casson Leighton [Sun, 24 May 2020 23:55:52 +0000 (00:55 +0100)]
spelling
Luke Kenneth Casson Leighton [Sun, 24 May 2020 22:00:59 +0000 (23:00 +0100)]
add comments for SPR pipe_data
Luke Kenneth Casson Leighton [Sun, 24 May 2020 21:43:27 +0000 (22:43 +0100)]
add SPR pipe_data.py
Luke Kenneth Casson Leighton [Sun, 24 May 2020 20:57:32 +0000 (21:57 +0100)]
over 80 char limit
Luke Kenneth Casson Leighton [Sun, 24 May 2020 20:46:56 +0000 (21:46 +0100)]
add test of reg output, for MFCRF and ISEL
Cesar Strauss [Sun, 24 May 2020 19:48:46 +0000 (16:48 -0300)]
Avoid overwriting the first vcd file with the second one
Cesar Strauss [Sun, 24 May 2020 19:44:12 +0000 (16:44 -0300)]
Rename the internal DFF of latchregisters to avoid conflict
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:47:53 +0000 (20:47 +0100)]
add gitignore for branch fu formal
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:23:54 +0000 (20:23 +0100)]
add OP_CMPB formal proof
Michael Nolan [Sun, 24 May 2020 19:16:28 +0000 (15:16 -0400)]
Assert that ctr is only written when needed
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:17:36 +0000 (20:17 +0100)]
split out Popcount into separate module: visually it interferes with readability of the fu logical main stage graphviz
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:05:55 +0000 (20:05 +0100)]
copy code for MTMSR from microwatt into comments
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:01:56 +0000 (20:01 +0100)]
add links for trap main stage
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:00:07 +0000 (20:00 +0100)]
add untested OP_MTMSR and OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:53:38 +0000 (19:53 +0100)]
update to new CSV files in submodule
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:49:30 +0000 (19:49 +0100)]
add MFMSR and MTMSRD enums to Function
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:30:56 +0000 (19:30 +0100)]
comment and add links to branch formal proof
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:20:18 +0000 (19:20 +0100)]
add copy of bpermd proof to logical formal proof (not nice but hey)
Luke Kenneth Casson Leighton [Sun, 24 May 2020 17:58:02 +0000 (18:58 +0100)]
track down overwrite of variable b
Michael Nolan [Sun, 24 May 2020 15:17:12 +0000 (11:17 -0400)]
Fix proof of bpermd module
Michael Nolan [Sun, 24 May 2020 15:15:54 +0000 (11:15 -0400)]
Fix bpermd and make tests pass
Michael Nolan [Sun, 24 May 2020 15:15:14 +0000 (11:15 -0400)]
Fix test_pipe_caller to conform to new Data() interface on outputs
Luke Kenneth Casson Leighton [Sun, 24 May 2020 15:05:00 +0000 (16:05 +0100)]
add stub regfiles.py
Luke Kenneth Casson Leighton [Sun, 24 May 2020 14:00:03 +0000 (15:00 +0100)]
hmm...
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:54:41 +0000 (14:54 +0100)]
add very rapid DummyALU for test purposes in MultiCompUnit
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:47:20 +0000 (14:47 +0100)]
comments on branch pipeline
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:36:28 +0000 (14:36 +0100)]
convert CR pipeline to Data.ok
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:07:02 +0000 (14:07 +0100)]
convert ALU to output Data on int reg
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:01:28 +0000 (14:01 +0100)]
convert logical to output Data on int reg
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:47:12 +0000 (13:47 +0100)]
start using Data in pipelines
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:09:54 +0000 (13:09 +0100)]
cleanup/code-munge on ALU main stage proof
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:03:53 +0000 (13:03 +0100)]
error in alu output stage formal proof setup
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:01:50 +0000 (13:01 +0100)]
output registers need to be Data type (consistently)
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:59:37 +0000 (12:59 +0100)]
spelling mistake in variable
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:54:55 +0000 (12:54 +0100)]
TODO mention OP_MTMSR/OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:51:56 +0000 (12:51 +0100)]
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 04:33:57 +0000 (05:33 +0100)]
move docstring to wiki for compunit
colepoirier [Sat, 23 May 2020 22:55:31 +0000 (15:55 -0700)]
Added branch and shift_rot imports to fu/compunits.py and created
BranchFunctionUnit and ShiftRotPipeSpec classes
Cesar Strauss [Sat, 23 May 2020 22:52:08 +0000 (19:52 -0300)]
Add a few test cases with zero_a set, in combination with imm_ok
Cesar Strauss [Sat, 23 May 2020 22:39:29 +0000 (19:39 -0300)]
Allow zero_a to be set when simulating an operation
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:24:07 +0000 (23:24 +0100)]
add input / output stage missing modules
Luke Kenneth Casson Leighton [Sat, 23 May 2020 20:47:17 +0000 (21:47 +0100)]
common function for op zero and op immed
Cesar Strauss [Sat, 23 May 2020 17:22:54 +0000 (14:22 -0300)]
Choose between RA (src1) and zero immediate, conditioned on zero_a
Luke Kenneth Casson Leighton [Sat, 23 May 2020 19:02:27 +0000 (20:02 +0100)]
update docs on compunits
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:44:13 +0000 (19:44 +0100)]
remove extraneous test_isel
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:22:47 +0000 (19:22 +0100)]
add comments
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:12:06 +0000 (19:12 +0100)]
document purpose of regspec module
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:05:31 +0000 (19:05 +0100)]
split out RegSpecs into separate module
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:53:11 +0000 (18:53 +0100)]
add TODO on multi-in multi-out Function Units
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:50:57 +0000 (18:50 +0100)]
split out RegSpec API into separate class (TODO: move to separate file)
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:40:49 +0000 (18:40 +0100)]
add notes on FunctionUnit API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:25:47 +0000 (18:25 +0100)]
make MultiCompUnit and testing ALU use regspec API and nmutil pipeline API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:24:45 +0000 (18:24 +0100)]
remove unneeded imports
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:08:08 +0000 (18:08 +0100)]
make demo/test ALU look like nmigen pipeline API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 15:21:21 +0000 (16:21 +0100)]
add stub DataMerger class