soc.git
4 years agold/st bus reduction test operational
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 14:24:06 +0000 (15:24 +0100)]
ld/st bus reduction test operational

4 years agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:06:03 +0000 (13:06 +0100)]
first test of down-converted load/store from 64 to 32 bit

4 years agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:05:45 +0000 (13:05 +0100)]
first test of down-converted load/store from 64 to 32 bit

4 years agoadd in WishboneDownConvert into LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:41:42 +0000 (12:41 +0100)]
add in WishboneDownConvert into LoadStoreUnitInterface

4 years agocomment formatting
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:00:15 +0000 (12:00 +0100)]
comment formatting

4 years agoremove default values
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:59:46 +0000 (11:59 +0100)]
remove default values

4 years agojust range(the_constant)
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:57:17 +0000 (11:57 +0100)]
just range(the_constant)

4 years agoMUL pipeline WIP: mullw and mullwu covered.
Samuel A. Falvo II [Fri, 21 Aug 2020 03:20:20 +0000 (20:20 -0700)]
MUL pipeline WIP: mullw and mullwu covered.

4 years agoMUL pipeline: account for overflow flags. WIP
Samuel A. Falvo II [Fri, 21 Aug 2020 02:54:20 +0000 (19:54 -0700)]
MUL pipeline: account for overflow flags.  WIP

4 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Fri, 21 Aug 2020 02:46:37 +0000 (19:46 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

4 years agodcache.py commit today and yesterday's progress (sorry for the delay,
Cole Poirier [Fri, 21 Aug 2020 02:44:41 +0000 (19:44 -0700)]
dcache.py commit today and yesterday's progress (sorry for the delay,
unexpected circumstances led me to not be able to commit yesterday)

4 years agoMUL pipeline proofs: mulli / mullw WIP.
Samuel A. Falvo II [Fri, 21 Aug 2020 01:32:17 +0000 (18:32 -0700)]
MUL pipeline proofs: mulli / mullw WIP.

4 years agoMUL pipeline proof: muldw(u)
Samuel A. Falvo II [Thu, 20 Aug 2020 23:58:11 +0000 (16:58 -0700)]
MUL pipeline proof: muldw(u)

4 years agoMUL pipeline proof: signed mulhw
Samuel A. Falvo II [Thu, 20 Aug 2020 22:30:17 +0000 (15:30 -0700)]
MUL pipeline proof: signed mulhw

4 years agostart wiring TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 18:47:39 +0000 (20:47 +0200)]
start wiring TestCachedMemoryPortInterface

4 years agotestcase refactoring
Tobias Platen [Thu, 20 Aug 2020 18:11:56 +0000 (20:11 +0200)]
testcase refactoring

4 years agoadd new class TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 17:34:32 +0000 (19:34 +0200)]
add new class TestCachedMemoryPortInterface

4 years agobugfix wishbone downconvert using wb sram 64-to-32 test
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 14:28:12 +0000 (15:28 +0100)]
bugfix wishbone downconvert using wb sram 64-to-32 test

4 years agoadd a wishbone upconverter
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 13:20:15 +0000 (14:20 +0100)]
add a wishbone upconverter

4 years agorename and document fields in shift_rot proof
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 22:03:54 +0000 (23:03 +0100)]
rename and document fields in shift_rot proof

4 years agocomments in dcache
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:58:12 +0000 (19:58 +0100)]
comments in dcache

4 years agomore subtle interactions between wishbone bus when there are delays,
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:02:30 +0000 (19:02 +0100)]
more subtle interactions between wishbone bus when there are delays,
LD/ST CompUnit and PortInterface

4 years agobit of a reorg of mul proof, tracking down missing
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:58 +0000 (07:24 +0100)]
bit of a reorg of mul proof, tracking down missing
Assume op.is_32bit == 0 for OP_MUL_H32

4 years agomove long mul tests to separate unit test
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:00 +0000 (07:24 +0100)]
move long mul tests to separate unit test

4 years agouse "Mask" class which is more gate-efficient than (1<<x)-1
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 04:45:21 +0000 (05:45 +0100)]
use "Mask" class which is more gate-efficient than (1<<x)-1

4 years agoWIP: OP_MUL proofs started.
Samuel A. Falvo II [Wed, 19 Aug 2020 04:12:19 +0000 (21:12 -0700)]
WIP: OP_MUL proofs started.

I am out of my league.  Cannot figure out how to make proof pass.
Committing latest incarnation of proof code.

4 years agoset up StageChain of 3 mul stages
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 00:15:33 +0000 (01:15 +0100)]
set up StageChain of 3 mul stages

4 years agofu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
Cole Poirier [Tue, 18 Aug 2020 21:15:20 +0000 (14:15 -0700)]
fu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
dividend from randint(0,1) to randint((-1 << 31), (1 << 31) - 1)

4 years agoadd testcase for LDSTSplitter using PortInterface
Tobias Platen [Tue, 18 Aug 2020 17:50:43 +0000 (19:50 +0200)]
add testcase for LDSTSplitter using PortInterface

4 years agofix spr state test
Luke Kenneth Casson Leighton [Tue, 18 Aug 2020 11:39:51 +0000 (12:39 +0100)]
fix spr state test

4 years agoadd comment in dcache.py
Luke Kenneth Casson Leighton [Tue, 18 Aug 2020 00:34:15 +0000 (01:34 +0100)]
add comment in dcache.py

4 years agodcache.py commit today's progress on translating dcache.vhdl
Cole Poirier [Mon, 17 Aug 2020 23:46:12 +0000 (16:46 -0700)]
dcache.py commit today's progress on translating dcache.vhdl

4 years agoCreate file experiment/wb_types.py to mirror microwatt wishbone_types.vhdl
Cole Poirier [Mon, 17 Aug 2020 23:44:55 +0000 (16:44 -0700)]
Create file experiment/wb_types.py to mirror microwatt wishbone_types.vhdl

4 years agomove Mask to nmutil
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 11:10:33 +0000 (12:10 +0100)]
move Mask to nmutil

4 years agoturn SelectableInt less/greater into signed versions.
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:59:49 +0000 (10:59 +0100)]
turn SelectableInt less/greater into signed versions.
may have ramifications as use of these operators assumes
unsigned

4 years agouse longer memtest in litex sim
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:59:04 +0000 (10:59 +0100)]
use longer memtest in litex sim

4 years agoadjust litex bios cmp test
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:58:20 +0000 (10:58 +0100)]
adjust litex bios cmp test

4 years agofix signed variants of cmp in alu
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:57:30 +0000 (10:57 +0100)]
fix signed variants of cmp in alu

4 years agoadd new cmp test for alu
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:56:48 +0000 (10:56 +0100)]
add new cmp test for alu

4 years agouse shift module in mmu. to be moved to nmutil
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:40:14 +0000 (10:40 +0100)]
use shift module in mmu. to be moved to nmutil

4 years agommu.py fix formatting 80 char limit
Cole Poirier [Sun, 16 Aug 2020 18:07:02 +0000 (11:07 -0700)]
mmu.py fix formatting 80 char limit

4 years agoattempting to track down bug in litex bios memtest
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 17:29:12 +0000 (18:29 +0100)]
attempting to track down bug in litex bios memtest

4 years agoread delay on getting regfile data
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 16:27:01 +0000 (17:27 +0100)]
read delay on getting regfile data

4 years agolimit debug reporting in litex sim to range of pc
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 14:28:15 +0000 (15:28 +0100)]
limit debug reporting in litex sim to range of pc

4 years agocmp test from litex bios
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 14:27:56 +0000 (15:27 +0100)]
cmp test from litex bios

4 years agoremove vhdl comments
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 13:25:41 +0000 (14:25 +0100)]
remove vhdl comments

4 years agouse simple one-line mask-generation
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 13:22:36 +0000 (14:22 +0100)]
use simple one-line mask-generation

4 years agofix LD/ST pimem issue with rising_edge detection
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 12:16:22 +0000 (13:16 +0100)]
fix LD/ST pimem issue with rising_edge detection

4 years agomissing vars, spelling corrections
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 10:25:55 +0000 (11:25 +0100)]
missing vars, spelling corrections

4 years agobig reorg, shuffle code to functions, makes the FSM clearer
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 10:11:48 +0000 (11:11 +0100)]
big reorg, shuffle code to functions, makes the FSM clearer

4 years agospelling error, move perm_ok to local
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:51:32 +0000 (10:51 +0100)]
spelling error, move perm_ok to local

4 years agomore comment removal
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:47:39 +0000 (10:47 +0100)]
more comment removal

4 years agomore remove comments
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:46:45 +0000 (10:46 +0100)]
more remove comments

4 years agoremoving more comments, tidyup
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:36:18 +0000 (10:36 +0100)]
removing more comments, tidyup

4 years agorestore incorrect removal of zero-Cat at LHS (should never do that)
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:21:09 +0000 (10:21 +0100)]
restore incorrect removal of zero-Cat at LHS (should never do that)

4 years agocontinue tidyup, comment removal/review. use byte_reverse function
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:20:04 +0000 (10:20 +0100)]
continue tidyup, comment removal/review.  use byte_reverse function

4 years agofix batch of syntax errors found by running mmu.py
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:05:30 +0000 (10:05 +0100)]
fix batch of syntax errors found by running mmu.py

4 years agobegin tidyup, removing comments after line-by-line review, remove MMU1, self.
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:01:51 +0000 (10:01 +0100)]
begin tidyup, removing comments after line-by-line review, remove MMU1, self.

4 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sat, 15 Aug 2020 23:49:16 +0000 (16:49 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

4 years agommu.py fix Cat() semantics fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c51
Cole Poirier [Sat, 15 Aug 2020 23:48:27 +0000 (16:48 -0700)]
mmu.py fix Cat() semantics fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c51

4 years agothanks to daveshah, added simulation of dram
Luke Kenneth Casson Leighton [Sat, 15 Aug 2020 23:20:00 +0000 (00:20 +0100)]
thanks to daveshah, added simulation of dram
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/84

this allows to track down a bug in the DDR3 memory test which is also
occurring in the FPGA version

4 years agommu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c54
Cole Poirier [Sat, 15 Aug 2020 23:18:29 +0000 (16:18 -0700)]
mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c54

4 years agommu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c53
Cole Poirier [Sat, 15 Aug 2020 23:17:14 +0000 (16:17 -0700)]
mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c53

4 years agommu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c52
Cole Poirier [Sat, 15 Aug 2020 23:14:00 +0000 (16:14 -0700)]
mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c52

4 years agorather big change to interaction between regfile and compunits on read
Luke Kenneth Casson Leighton [Sat, 15 Aug 2020 21:54:50 +0000 (22:54 +0100)]
rather big change to interaction between regfile and compunits on read
regfiles are now sync-delayed by one clock from "ren".  this means that
a read-request has to be fired off then excluded from the PriorityPicker,
whilst waiting for the output to arrive on the next clock.  *then*
the "go read" signal can be fired, which gets the data (arriving 1 cycle
late from the regfile) "in sync" with its "go read"

4 years agoclear compalu data latch always on issue
Luke Kenneth Casson Leighton [Sat, 15 Aug 2020 21:33:25 +0000 (22:33 +0100)]
clear compalu data latch always on issue

4 years agoDemonstrates string traces
Cesar Strauss [Fri, 14 Aug 2020 11:25:36 +0000 (08:25 -0300)]
Demonstrates string traces

When declaring a Signal, you can pass a custom decoder that translates
the Signal logic level to a string. nMigen uses this internally to
display Enum traces, but it is available for general use.

Some applications are:
1) Display a string when a signal is at high level, otherwise show a
single horizontal line. Useful to draw attention to a time interval.
2) Display the stages of a unit test
3) Display arbitrary debug statements along the timeline.

4 years agoDemonstrates adding extra debug signals traces to the dump file
Cesar Strauss [Fri, 14 Aug 2020 11:06:49 +0000 (08:06 -0300)]
Demonstrates adding extra debug signals traces to the dump file

At simulation time, you can declare a new signal, and use it inside
the test case, as any other signal. By including it in the "traces"
parameter of Simulator.write_vcd, it is included in the trace dump file.

Useful for adding "printf" style debugging for GTKWave.

4 years agoDemonstrates creating stylish GTKWave "save" files from python
Cesar Strauss [Thu, 13 Aug 2020 22:40:35 +0000 (19:40 -0300)]
Demonstrates creating stylish GTKWave "save" files from python

This is inspired on the use of the vcd.gtkw module in nMigen, used
internally to create "save" files of selected Signals, for
"Simulator.write_vcd".

However, the vcd.gtkw module exposes a great deal of extra possibilities,
like:

1) Individual trace colors.
For instance, use different color styles for input, output, debug and
internal traces.
2) Numeric bases besides the default hex.
3) Collapsible trace groups
Useful to hide and show, at once, groups of debug, internal and
sub-module traces.
Select the opening or closing brace, then use the T key.
4) Comments in the signal names pane
5) Change the displayed name of a trace
6) Sane default for initial zoom level
7) Place markers on interesting places
8) Put the generating file name as a comment in the file

4 years agoremove latchregister, use sync to capture compunit results
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 23:03:49 +0000 (00:03 +0100)]
remove latchregister, use sync to capture compunit results

4 years agoha! "state" (pc, msr) not properly passed to core
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 20:32:09 +0000 (21:32 +0100)]
ha! "state" (pc, msr) not properly passed to core

4 years agodrop in insn_state synchronously in issuer, at same time as insn
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 20:03:40 +0000 (21:03 +0100)]
drop in insn_state synchronously in issuer, at same time as insn

4 years agosubmodule update
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:45:31 +0000 (20:45 +0100)]
submodule update

4 years agohrfid unit test sets up HSRR0 and HSRR1
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:45:22 +0000 (20:45 +0100)]
hrfid unit test sets up HSRR0 and HSRR1

4 years agobad hack to get HSRR0/1 to be "same" as SRR0/1
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:44:59 +0000 (20:44 +0100)]
bad hack to get HSRR0/1 to be "same" as SRR0/1

4 years agobug in isa parser not recognising MSR as declared variable
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:44:35 +0000 (20:44 +0100)]
bug in isa parser not recognising MSR as declared variable

4 years agohack to get hrfid not to alter msr 51
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:43:56 +0000 (20:43 +0100)]
hack to get hrfid not to alter msr 51

4 years agostop trying to read swap files
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:43:08 +0000 (20:43 +0100)]
stop trying to read swap files

4 years agosync on alu results in compalu
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 19:23:34 +0000 (20:23 +0100)]
sync on alu results in compalu

4 years agoupdate submodule, add hrfid
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 17:25:17 +0000 (18:25 +0100)]
update submodule, add hrfid

4 years agoupdate submodule, add hrfid
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 17:23:33 +0000 (18:23 +0100)]
update submodule, add hrfid

4 years agofinally, fix decoder combinatorial loop
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 17:18:48 +0000 (18:18 +0100)]
finally, fix decoder combinatorial loop

4 years agofix test_compunit.py after moving decoder rdflags function
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 17:18:18 +0000 (18:18 +0100)]
fix test_compunit.py after moving decoder rdflags function

4 years agoadd hrfid unit test
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 17:17:48 +0000 (18:17 +0100)]
add hrfid unit test

4 years agosync up the core decode-execute state,
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 14:48:05 +0000 (15:48 +0100)]
sync up the core decode-execute state,
fix bug when pulling reset

4 years agomove instruction decoder out of core
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 14:26:10 +0000 (15:26 +0100)]
move instruction decoder out of core

4 years agomove regspec / rdflag decoding functions out of PowerDecode2
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 14:05:05 +0000 (15:05 +0100)]
move regspec / rdflag decoding functions out of PowerDecode2

4 years agosort out instruction stop/cancel when adding a new issuer FSM state
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 13:57:54 +0000 (14:57 +0100)]
sort out instruction stop/cancel when adding a new issuer FSM state

4 years agoput multi-ports back (for read) on int and fast regfiles
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 11:59:01 +0000 (12:59 +0100)]
put multi-ports back (for read) on int and fast regfiles

4 years agoreduce decoder pathways when exception occurs
Luke Kenneth Casson Leighton [Fri, 14 Aug 2020 11:10:06 +0000 (12:10 +0100)]
reduce decoder pathways when exception occurs

4 years agodivide shiftrot pipeline into 2 (simple last)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:26:00 +0000 (00:26 +0100)]
divide shiftrot pipeline into 2 (simple last)

4 years agodivide alu pipeline into 2 (simple last)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:25:36 +0000 (00:25 +0100)]
divide alu pipeline into 2 (simple last)

4 years agodivide logical pipe into 2 (simple phase last)
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 23:19:34 +0000 (00:19 +0100)]
divide logical pipe into 2 (simple phase last)

4 years agorunning the simulator works!
Jacob Lifshay [Fri, 14 Aug 2020 04:22:01 +0000 (21:22 -0700)]
running the simulator works!

4 years agoadd --cpu=libresoc to Makefile
Jacob Lifshay [Thu, 13 Aug 2020 23:18:03 +0000 (16:18 -0700)]
add --cpu=libresoc to Makefile

4 years agofix dmi reg read
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:44:29 +0000 (22:44 +0100)]
fix dmi reg read

4 years agocode-shuffle
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:23:18 +0000 (22:23 +0100)]
code-shuffle

4 years agoremove use of latchregigister, replace with sync on rd.go_i
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 21:23:08 +0000 (22:23 +0100)]
remove use of latchregigister, replace with sync on rd.go_i

4 years agosync on pc writing when changed
Luke Kenneth Casson Leighton [Thu, 13 Aug 2020 20:33:25 +0000 (21:33 +0100)]
sync on pc writing when changed

4 years agodcache.py add initial imports
Cole Poirier [Thu, 13 Aug 2020 19:05:10 +0000 (12:05 -0700)]
dcache.py add initial imports