soc.git
3 years agoanother batch of ready/valid i/o prefix-suffix swaps
Luke Kenneth Casson Leighton [Fri, 3 Sep 2021 07:13:14 +0000 (08:13 +0100)]
another batch of ready/valid i/o prefix-suffix swaps

3 years agoanooother valid_o to convert to o_valid
Luke Kenneth Casson Leighton [Tue, 31 Aug 2021 20:27:08 +0000 (21:27 +0100)]
anooother valid_o to convert to o_valid

3 years agoupdate ready/valid in shift_rot test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 31 Aug 2021 20:20:02 +0000 (21:20 +0100)]
update ready/valid in shift_rot test_pipe_caller

3 years agofix test_all_values_covered, missed import when moving test cases to openpower.git
Jacob Lifshay [Tue, 31 Aug 2021 04:54:04 +0000 (21:54 -0700)]
fix test_all_values_covered, missed import when moving test cases to openpower.git

3 years agoupdate ready/valid i/o_ prefix in div test helper.py
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 16:38:31 +0000 (17:38 +0100)]
update ready/valid i/o_ prefix in div test helper.py

3 years agofix ready/valid i/o prefix in ALU test
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 14:33:41 +0000 (15:33 +0100)]
fix ready/valid i/o prefix in ALU test

3 years agofix CR tests valid/ready naming
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 12:26:49 +0000 (13:26 +0100)]
fix CR tests valid/ready naming

3 years agomissed valid/ready_i/o to o/i_ conversion
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 11:39:26 +0000 (12:39 +0100)]
missed valid/ready_i/o to o/i_ conversion

3 years agomissed valid/ready_i/o to o/i_ conversion
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 11:36:54 +0000 (12:36 +0100)]
missed valid/ready_i/o to o/i_ conversion

3 years agounnecessary signal rename ivalid_i to ii_valid (reverting)
Luke Kenneth Casson Leighton [Sun, 29 Aug 2021 21:00:59 +0000 (22:00 +0100)]
unnecessary signal rename ivalid_i to ii_valid (reverting)

3 years agoreplace data_o with o_data and data_i with i_data as well
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 11:53:06 +0000 (12:53 +0100)]
replace data_o with o_data and data_i with i_data as well
a little more care involved here due to names such as st_data_o
and others

3 years agobig rename, global/search/replace of ready_o with o_ready and the other
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 10:22:14 +0000 (11:22 +0100)]
big rename, global/search/replace of ready_o with o_ready and the other
> 4 signals as well, valid_i -> i_valid
> https://libera.irclog.whitequark.org/nmigen/2021-08-24#30728292;
> to be consistent with nmigen standards

3 years agoremove svanalysis from Makefile, it is now part of openpower-isa
Luke Kenneth Casson Leighton [Sun, 22 Aug 2021 09:43:26 +0000 (10:43 +0100)]
remove svanalysis from Makefile, it is now part of openpower-isa

3 years agofix "link addr-go direct to rel"
Tobias Platen [Tue, 17 Aug 2021 18:06:10 +0000 (20:06 +0200)]
fix "link addr-go direct to rel"

3 years agoEnable LD/ST exception test case
Cesar Strauss [Tue, 17 Aug 2021 11:37:47 +0000 (08:37 -0300)]
Enable LD/ST exception test case

It helps for implementing exception handling in TestIssuer

3 years agoClear operand latch on a terminating condition
Cesar Strauss [Tue, 17 Aug 2021 11:11:19 +0000 (08:11 -0300)]
Clear operand latch on a terminating condition

3 years agoAdd exc_o.happened to the conditions for terminating the CompUnit FSM
Cesar Strauss [Tue, 17 Aug 2021 10:18:00 +0000 (07:18 -0300)]
Add exc_o.happened to the conditions for terminating the CompUnit FSM

Otherwise, a failed load will hang indefinitely, waiting for data that
never comes.

3 years agoFix activation of cancel signal
Cesar Strauss [Tue, 17 Aug 2021 10:13:04 +0000 (07:13 -0300)]
Fix activation of cancel signal

As an active low signal, the conditions to cancel must be ANDed together.
Being active high, exc_o.happened must be inverted.

3 years agoAdjust PortInterface traces according to MMU option
Cesar Strauss [Mon, 16 Aug 2021 21:39:39 +0000 (18:39 -0300)]
Adjust PortInterface traces according to MMU option

The hierarchy of PortInterface changes when the MMU is present. Set the
correct module path, so the traces don't vanish in the GTKWave document.

3 years agofix renamed symbols
Tobias Platen [Mon, 16 Aug 2021 18:25:14 +0000 (20:25 +0200)]
fix renamed symbols

3 years agoadd WIP DCBZTestCase
Tobias Platen [Mon, 16 Aug 2021 18:02:06 +0000 (20:02 +0200)]
add WIP DCBZTestCase

3 years agoGitLab-CI: Only run tests in src/
Jonathan Neuschäfer [Wed, 11 Aug 2021 07:46:11 +0000 (09:46 +0200)]
GitLab-CI: Only run tests in src/

Specifically, the tests in unused_please_ignore_completely/ should not
be run. Some of them would fail, but it doesn't matter.

3 years agomove unused directory out of src, to indicate "ignore completely"
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:46:55 +0000 (18:46 +0100)]
move unused directory out of src, to indicate "ignore completely"

3 years agoimport setup_i_memory from soc.simple.test.test_runner
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:25:34 +0000 (00:25 +0200)]
import setup_i_memory from soc.simple.test.test_runner

This function was moved in commit 8482a3ed
("split out TestRunner into separate module").

3 years agosoc.simple.test: Rename setup_test_memory to avoid nosetest calling it
Jonathan Neuschäfer [Sun, 1 Aug 2021 17:08:50 +0000 (19:08 +0200)]
soc.simple.test: Rename setup_test_memory to avoid nosetest calling it

3 years agoRename test_dcache, which can't be invoked by test runners
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:43:26 +0000 (00:43 +0200)]
Rename test_dcache, which can't be invoked by test runners

Functions named *test_* are invoked by test runners, such as nosetests,
but test_dcache was not written with this behavior in mind. Rename it to
avoid invocation.

Maybe the main block at the end of a file should now be converted into a
test that *is* invoked by test runners.

3 years agosimulator/test_sim.py should not have been added
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:39:27 +0000 (18:39 +0100)]
simulator/test_sim.py should not have been added

3 years agopartial fix for src/soc/experiment/compldst_multi.py
Tobias Platen [Sat, 31 Jul 2021 16:49:45 +0000 (18:49 +0200)]
partial fix for src/soc/experiment/compldst_multi.py

3 years agopartially fix unit test in compldst_multi.py
Tobias Platen [Fri, 30 Jul 2021 18:59:24 +0000 (20:59 +0200)]
partially fix unit test in compldst_multi.py

3 years agocompldst_multi: add debug output for dcbz
Tobias Platen [Mon, 26 Jul 2021 18:42:21 +0000 (20:42 +0200)]
compldst_multi: add debug output for dcbz

3 years agoadd test_issuer_dcache.py
Tobias Platen [Sat, 24 Jul 2021 11:25:49 +0000 (13:25 +0200)]
add test_issuer_dcache.py

3 years agoldst: cleanup debug outputs
Tobias Platen [Fri, 23 Jul 2021 18:49:52 +0000 (20:49 +0200)]
ldst: cleanup debug outputs

3 years agotest_dcbz_pi.py: dcbz now working
Tobias Platen [Fri, 23 Jul 2021 18:48:37 +0000 (20:48 +0200)]
test_dcbz_pi.py: dcbz now working

3 years agorevert accidential delete in test_pi2ls.py causing tests to break
Tobias Platen [Wed, 21 Jul 2021 19:04:24 +0000 (21:04 +0200)]
revert accidential delete in test_pi2ls.py causing tests to break

3 years agotest_dcbz_pi.py: do not use problem state
Tobias Platen [Wed, 21 Jul 2021 18:02:48 +0000 (20:02 +0200)]
test_dcbz_pi.py: do not use problem state

3 years agoupdate pi_dcbz function
Tobias Platen [Wed, 21 Jul 2021 17:57:55 +0000 (19:57 +0200)]
update pi_dcbz function

3 years agosrc/soc/config/test/test_pi2ls.py: add more debug outputs
Tobias Platen [Mon, 19 Jul 2021 19:01:38 +0000 (21:01 +0200)]
src/soc/config/test/test_pi2ls.py: add more debug outputs

3 years agotest_dcbz_pi.py: more work on unit test
Tobias Platen [Mon, 19 Jul 2021 18:38:05 +0000 (20:38 +0200)]
test_dcbz_pi.py: more work on unit test

3 years agoupdate TestRunner, SVSTATE is now a class that inherits from SelectableInt
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 12:51:49 +0000 (13:51 +0100)]
update TestRunner, SVSTATE is now a class that inherits from SelectableInt
rather than *contains* a SelectableInt

3 years agoupdate SVSTATE to 64 bit length (fortunately very easy)
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 19:07:02 +0000 (20:07 +0100)]
update SVSTATE to 64 bit length (fortunately very easy)

3 years agoadd more debug outputs, pass dcbz to loadstore/dcache
Tobias Platen [Wed, 14 Jul 2021 18:38:11 +0000 (20:38 +0200)]
add more debug outputs, pass dcbz to loadstore/dcache

3 years agodcache: improve debug output
Tobias Platen [Wed, 14 Jul 2021 18:28:31 +0000 (20:28 +0200)]
dcache: improve debug output

3 years agouse standard create_pdecode in TestRunner
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 12:38:03 +0000 (13:38 +0100)]
use standard create_pdecode in TestRunner

3 years agouse default decoder, do not pass one in.
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:11:07 +0000 (22:11 +0100)]
use default decoder, do not pass one in.
inside PowerDecoder2, create default decoder with new "conditions"

3 years agomore work on test_dcbz_pi.py
Tobias Platen [Sun, 11 Jul 2021 16:57:10 +0000 (18:57 +0200)]
more work on test_dcbz_pi.py

3 years agopass self.pi.is_dcbz to request
Tobias Platen [Sun, 11 Jul 2021 16:18:13 +0000 (18:18 +0200)]
pass self.pi.is_dcbz to request

3 years agoimplement pi_dcbz
Tobias Platen [Sun, 11 Jul 2021 15:50:25 +0000 (17:50 +0200)]
implement pi_dcbz

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sun, 11 Jul 2021 15:38:04 +0000 (17:38 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agoadd test_dcbz_pi.py (skeleton only)
Tobias Platen [Sun, 11 Jul 2021 15:37:22 +0000 (17:37 +0200)]
add test_dcbz_pi.py (skeleton only)

3 years agoShow some usage of PortInterface in action
Cesar Strauss [Sat, 10 Jul 2021 21:53:22 +0000 (18:53 -0300)]
Show some usage of PortInterface in action

3 years agoAdd new traces to the GTKWave document
Cesar Strauss [Sat, 10 Jul 2021 17:25:16 +0000 (14:25 -0300)]
Add new traces to the GTKWave document

The new traces are related to the state latches, operand fetch and ALU
address generation.

3 years agoAdd operand producers to the parallel LDST Compunit test case
Cesar Strauss [Sat, 10 Jul 2021 17:17:17 +0000 (14:17 -0300)]
Add operand producers to the parallel LDST Compunit test case

Code from the parallel ALU Compunit test case was successfully reused.
Result consumers are to be added later.
The simulation now runs through the operand fetch phase and the address
ALU phase.

3 years agoDetect unexpected operand fetches and produced results
Cesar Strauss [Sat, 10 Jul 2021 16:47:19 +0000 (13:47 -0300)]
Detect unexpected operand fetches and produced results

When some operands are not used (zero_a and/or imm_ok), raise an error as
soon as rel_o is asserted. Likewise, for results (when not in RA update
mode).

3 years agoStart of a GTKWave document for the LDST CompUnit parallel unit test
Cesar Strauss [Wed, 7 Jul 2021 09:36:50 +0000 (06:36 -0300)]
Start of a GTKWave document for the LDST CompUnit parallel unit test

3 years agoBeginning of a class to make a parallel test case for LDSTCompUnit
Cesar Strauss [Sun, 4 Jul 2021 21:00:27 +0000 (18:00 -0300)]
Beginning of a class to make a parallel test case for LDSTCompUnit

For now it just issues an operation. Later it will setup producers and
consumers for input/output operands and the port interface.

3 years agocut down on time by uncommenting data not needed, adding documentation
Tobias Platen [Wed, 30 Jun 2021 17:41:01 +0000 (19:41 +0200)]
cut down on time by uncommenting data not needed, adding documentation

3 years agoupdate ldst test case by adding precise timing
Tobias Platen [Mon, 28 Jun 2021 17:44:36 +0000 (19:44 +0200)]
update ldst test case by adding precise timing

3 years agopropagate new use_svp64_ldst_dec mode through TestCore and TestIssuer
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 14:52:25 +0000 (15:52 +0100)]
propagate new use_svp64_ldst_dec mode through TestCore and TestIssuer

3 years agoadd an explicit PowerDecoder.is_svp64_mode flag to help with detection
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 12:26:19 +0000 (13:26 +0100)]
add an explicit PowerDecoder.is_svp64_mode flag to help with detection

3 years agodcache: add debug output
Tobias Platen [Sun, 20 Jun 2021 17:31:34 +0000 (19:31 +0200)]
dcache: add debug output

3 years agoupdate test_ldst_pi.py
Tobias Platen [Sun, 20 Jun 2021 16:00:22 +0000 (18:00 +0200)]
update test_ldst_pi.py

3 years agouncomment test_dcache_random
Tobias Platen [Fri, 18 Jun 2021 18:09:54 +0000 (20:09 +0200)]
uncomment test_dcache_random

3 years agosrc/soc/fu/ldst/loadstore.py: keep data for the whole cycle
Tobias Platen [Fri, 18 Jun 2021 17:40:05 +0000 (19:40 +0200)]
src/soc/fu/ldst/loadstore.py: keep data for the whole cycle

3 years agoupdate testcase for ldst
Tobias Platen [Mon, 14 Jun 2021 18:02:49 +0000 (20:02 +0200)]
update testcase for ldst

3 years agowhoops Popcount datalen too big (wasted bits). reduce
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 19:10:16 +0000 (20:10 +0100)]
whoops Popcount datalen too big (wasted bits). reduce

3 years agogit submodule update
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:51:14 +0000 (16:51 +0100)]
git submodule update

3 years agodisconnect pll clock, connected in peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:08:25 +0000 (16:08 +0100)]
disconnect pll clock, connected in peripheral interconnect

3 years agoadd in/out of ref_clk and pllclk_clk when PLL enabled
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:32:26 +0000 (14:32 +0100)]
add in/out of ref_clk and pllclk_clk when PLL enabled

3 years agoStart a new self-contained test suite for LDSTCompUnit
Cesar Strauss [Sun, 6 Jun 2021 22:00:46 +0000 (19:00 -0300)]
Start a new self-contained test suite for LDSTCompUnit

The idea is to use parallel processes, like on the new ALU CompUnit tests.
In this case, it will include PortInterface emulation as well.
The current goal is to ensure that exception support is properly
implemented.

3 years agocomment out domains that have already been created
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:36:40 +0000 (16:36 +0100)]
comment out domains that have already been created

3 years agono, do not assign clock to clock!
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:48:14 +0000 (15:48 +0100)]
no, do not assign clock to clock!

3 years agorename ref to ref_v in PLL due to ref being a verilog keyword
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:42:32 +0000 (15:42 +0100)]
rename ref to ref_v in PLL due to ref being a verilog keyword

3 years agosort out PLL domains but bypass PLL due to lack of time
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:41:33 +0000 (15:41 +0100)]
sort out PLL domains but bypass PLL due to lack of time

3 years agouse DomainRenamer on all sub-components of TestIssuer
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:48:32 +0000 (13:48 +0100)]
use DomainRenamer on all sub-components of TestIssuer
except for JTAG and DMI

3 years agomake core_rst a member of TestIssuerInternal
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:02:59 +0000 (13:02 +0100)]
make core_rst a member of TestIssuerInternal

3 years agotest_ldst_pi.py: add new test case
Tobias Platen [Tue, 1 Jun 2021 18:23:37 +0000 (20:23 +0200)]
test_ldst_pi.py: add new test case

3 years agotest_ldst_pi.py: first version of test_dcache_random()
Tobias Platen [Sat, 29 May 2021 18:46:18 +0000 (20:46 +0200)]
test_ldst_pi.py: first version of test_dcache_random()

3 years agotest_ldst_pi.py: more test_dcache_regression()
Tobias Platen [Sat, 29 May 2021 18:10:15 +0000 (20:10 +0200)]
test_ldst_pi.py: more test_dcache_regression()

3 years agoadjust PLL connections looking for coriolis2 issue
Luke Kenneth Casson Leighton [Thu, 27 May 2021 17:21:16 +0000 (18:21 +0100)]
adjust PLL connections looking for coriolis2 issue

3 years agocorrections on spblock ack
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:04:10 +0000 (13:04 +0100)]
corrections on spblock ack

3 years agoclassic wishbone mode: must not do ack if already acked
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:01:42 +0000 (13:01 +0100)]
classic wishbone mode: must not do ack if already acked

3 years agoarse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:10:30 +0000 (16:10 +0100)]
arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2

3 years agoremove err feature from sram4k wb
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:09:58 +0000 (16:09 +0100)]
remove err feature from sram4k wb

3 years agoadd ldst PortInterface misalign unit test (underway)
Luke Kenneth Casson Leighton [Wed, 26 May 2021 13:22:45 +0000 (14:22 +0100)]
add ldst PortInterface misalign unit test (underway)

3 years agorename PLL signals
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:31:31 +0000 (12:31 +0100)]
rename PLL signals

3 years agotest_ldst_pi.py: fix race condition causing early stop
Tobias Platen [Tue, 25 May 2021 19:00:41 +0000 (21:00 +0200)]
test_ldst_pi.py: fix race condition causing early stop

3 years agowait_ldok: add debug output count
Tobias Platen [Tue, 25 May 2021 17:22:46 +0000 (19:22 +0200)]
wait_ldok: add debug output count

3 years agowhoops sort out name of SPBlock RAM
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:21:00 +0000 (18:21 +0100)]
whoops sort out name of SPBlock RAM

3 years agochange name of submodule to real_pll
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:05:10 +0000 (18:05 +0100)]
change name of submodule to real_pll

3 years agomatch up PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:55:09 +0000 (12:55 +0100)]
match up PLL names

3 years agoRemove redundant build step
Cesar Strauss [Sat, 22 May 2021 21:12:48 +0000 (18:12 -0300)]
Remove redundant build step

The pywriter script has already ran, as part of the openpower-isa install.

3 years agoInclude missing step in automated build
Cesar Strauss [Sat, 22 May 2021 21:10:02 +0000 (18:10 -0300)]
Include missing step in automated build

The newly added pyfnwriter script needs to run just before pywriter.

3 years agoMove the reset code outside of the sub-test
Cesar Strauss [Sat, 22 May 2021 20:31:00 +0000 (17:31 -0300)]
Move the reset code outside of the sub-test

Even if a sub-test fails, the core still needs to be reset.
This code does not check any assertions, so it's safe to move it outside.

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:32 +0000 (11:50 +0100)]
update submodule

3 years agoupdate PLL to use Instance
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:25 +0000 (11:50 +0100)]
update PLL to use Instance

3 years agotest_ldst_pi.py: add dcache regression and random test from test_dcache.py
Tobias Platen [Sat, 15 May 2021 17:10:33 +0000 (19:10 +0200)]
test_ldst_pi.py: add dcache regression and random test from test_dcache.py

3 years agoadd radix MMU "miss" test
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:47:38 +0000 (20:47 +0100)]
add radix MMU "miss" test

3 years agoclear out request data on return to idle
Luke Kenneth Casson Leighton [Fri, 14 May 2021 12:04:17 +0000 (13:04 +0100)]
clear out request data on return to idle

3 years agosort out LoadStore1 misalignment FSM, also required test function pi_ld
Luke Kenneth Casson Leighton [Fri, 14 May 2021 11:09:55 +0000 (12:09 +0100)]
sort out LoadStore1 misalignment FSM, also required test function pi_ld
to be modified to understand exceptions.  pi_st TODO

3 years agoremove minerva units previously missed in cleanout
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:36:19 +0000 (11:36 +0100)]
remove minerva units previously missed in cleanout