Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 13:31:38 +0000 (14:31 +0100)]
adding bus data width of 64 in litex sim doesnt work
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 11:32:45 +0000 (12:32 +0100)]
add div test cases into test_issuer.py
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 09:29:44 +0000 (10:29 +0100)]
add div FSM as default for test_issuer in verilog and ilang gen
Jacob Lifshay [Wed, 5 Aug 2020 03:44:44 +0000 (20:44 -0700)]
Fixed div pipe with FSM
FU unit test was checking the output one cycle too late
See also https://bugs.libre-soc.org/show_bug.cgi?id=449
Cole Poirier [Wed, 5 Aug 2020 00:09:09 +0000 (17:09 -0700)]
Add case_all to MUL unit tests, remove duplicate test case_4_mullw_rand
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 21:57:00 +0000 (22:57 +0100)]
read/set pc outside of FSM so that DMI interface can get at it
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 18:18:24 +0000 (19:18 +0100)]
swap over byte-reverse if/else in LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 16:56:12 +0000 (17:56 +0100)]
tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:53:59 +0000 (16:53 +0100)]
whitespace after autopep8 messed up
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:42:54 +0000 (16:42 +0100)]
msr and pc moved to "state" in PowerDecode2
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:38:43 +0000 (16:38 +0100)]
whoops must output NIA not PC to debug DMI query in test_issuer
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:04:43 +0000 (16:04 +0100)]
allow instruction to run if initiated whilst "stopped" requested
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 14:15:52 +0000 (15:15 +0100)]
cycle through INT regs, read and debug in litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 12:20:09 +0000 (13:20 +0100)]
add DMI debug interface to libresoc litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 12:06:06 +0000 (13:06 +0100)]
single-step and print out PC using DMI in litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 11:44:13 +0000 (12:44 +0100)]
get litex sim to kick off a "STEP" via the DMI interface every N cycles
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 11:07:26 +0000 (12:07 +0100)]
connect up a DMI FSM to litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:41:45 +0000 (10:41 +0100)]
more remove wildcard imports
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:20:15 +0000 (10:20 +0100)]
do not use wildcard imports
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:16:39 +0000 (10:16 +0100)]
adding litex sim experimentation.
not keen on doing this: adding microwatt.v however it is an important
test and a massive dependency chain needed for generating it
Samuel A. Falvo II [Tue, 4 Aug 2020 02:54:16 +0000 (19:54 -0700)]
Remove XXX; this seems done otherwise.
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:55:51 +0000 (20:55 +0100)]
add quick demo/test of reading DMI reg 9
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:24:03 +0000 (20:24 +0100)]
add extra port for debug read of int regs via DMI
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:19:17 +0000 (20:19 +0100)]
pass state (MSR/PC) around between PowerDecode2, DMI, and TestIssuer
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:08:49 +0000 (20:08 +0100)]
https://bugs.libre-soc.org/show_bug.cgi?id=446
Revert "LDSTSplitter: report exception"
This reverts commit
16f3cca9062314475a9039c96ffa1bc97122a408.
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:04:56 +0000 (20:04 +0100)]
use new soc.config.state CoreState class in DMI and test_issuer
Tobias Platen [Mon, 3 Aug 2020 18:37:47 +0000 (20:37 +0200)]
LDSTSplitter: report exception
Tobias Platen [Mon, 3 Aug 2020 18:06:25 +0000 (20:06 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Mon, 3 Aug 2020 18:06:15 +0000 (20:06 +0200)]
TstDataMerger2
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 17:02:52 +0000 (18:02 +0100)]
change over to DMI debug start/stop interface
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 17:02:13 +0000 (18:02 +0100)]
move debug to record
Samuel A. Falvo II [Mon, 3 Aug 2020 15:17:55 +0000 (08:17 -0700)]
WIP: check MB > ME and select mask appropriately
Luke Kenneth Casson Leighton [Sun, 2 Aug 2020 15:21:56 +0000 (16:21 +0100)]
convert microwatt core_debug.vhdl to nmigen
Luke Kenneth Casson Leighton [Sun, 2 Aug 2020 09:16:18 +0000 (10:16 +0100)]
add debug dir
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 13:00:00 +0000 (14:00 +0100)]
add quick test of litex bios IMM64 macro
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 11:05:07 +0000 (12:05 +0100)]
add rlwnm test showing that shift rot OP_RLC proof is incorrect.
using same values as inputs from the proof
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 10:24:25 +0000 (11:24 +0100)]
line-length / whitespace
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 09:49:08 +0000 (10:49 +0100)]
expand out for-loop setting up input record subset
this to help in formal proof shiftrot analysis
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:52:11 +0000 (17:52 +0100)]
reorg DecodeB in power_decoder2.py to sign-extend immediates
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:31:21 +0000 (17:31 +0100)]
add more instructions to litex trampoline test (not tested)
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:30:56 +0000 (17:30 +0100)]
restrict external port list further in test_issuer
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:30:25 +0000 (17:30 +0100)]
missed go_i/rel_o rename
Samuel A. Falvo II [Fri, 31 Jul 2020 16:53:41 +0000 (09:53 -0700)]
WIP: more debugging signals for inspection
Samuel A. Falvo II [Thu, 30 Jul 2020 23:18:49 +0000 (16:18 -0700)]
WIP: rlwinm/rlwnm/rlwimi-type proofs
Been trying to wittle away at this for several days now, without luck.
What am I missing?!
Tobias Platen [Thu, 30 Jul 2020 17:40:09 +0000 (19:40 +0200)]
begin work on TestCase for two DataMergers/Cache
Tobias Platen [Thu, 30 Jul 2020 16:57:46 +0000 (18:57 +0200)]
add CacheRecord
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 14:12:05 +0000 (15:12 +0100)]
core_start/stop/endian were inverted (output)
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:27:55 +0000 (13:27 +0100)]
ha! have to explicitly specify the ports when writing out to ilang or verilog
this gives unused signals that default to a non-zero value to inherently
set by default to that value.
exposing them externally via ports makes setting them the *users*
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:21:43 +0000 (13:21 +0100)]
add trampoline test from litex
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:19:07 +0000 (13:19 +0100)]
set sel line in minerva instruction fetch
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 09:39:43 +0000 (10:39 +0100)]
ha! found source of XICS test bug: wishbone stb was being left HI
for more than one cycle in the *unit* test, thereby putting spurious
data onto the bus and corrupting transactions
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 17:48:14 +0000 (18:48 +0100)]
more exploratory testing of XICS, joining ICP and ICS together
Tobias Platen [Wed, 29 Jul 2020 16:55:54 +0000 (18:55 +0200)]
modified LDSTSplitter to conform to PortInterface
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 16:22:29 +0000 (17:22 +0100)]
forgot to rename ad/st in LDSTCompUnitRecord
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 15:19:08 +0000 (16:19 +0100)]
bit of a big change: add prefixes "cu_" to all CompUnit management signals
also change go/rel to go_i and rel_o at the same time
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 13:23:18 +0000 (14:23 +0100)]
start on test joining XICS ICS to ICP
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 13:08:32 +0000 (14:08 +0100)]
tidyup XICS, identify (potential?) bug?
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 10:58:59 +0000 (11:58 +0100)]
move CR test out of subtest indentation
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 10:54:19 +0000 (11:54 +0100)]
move SHIFTROT test out of subtest indentation
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 10:49:16 +0000 (11:49 +0100)]
move actual ALU test out of subTest indentation just like for div
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 10:42:05 +0000 (11:42 +0100)]
whitespace
Jacob Lifshay [Wed, 29 Jul 2020 00:44:57 +0000 (17:44 -0700)]
clean up branch test_pipe_caller
Jacob Lifshay [Wed, 29 Jul 2020 00:40:56 +0000 (17:40 -0700)]
clean up alu test_pipe_caller
Jacob Lifshay [Wed, 29 Jul 2020 00:38:58 +0000 (17:38 -0700)]
add __init__.py to all source directories
Jacob Lifshay [Wed, 29 Jul 2020 00:27:44 +0000 (17:27 -0700)]
clean up some tests
Jacob Lifshay [Wed, 29 Jul 2020 00:26:16 +0000 (17:26 -0700)]
format some tests
Jacob Lifshay [Wed, 29 Jul 2020 00:23:02 +0000 (17:23 -0700)]
add code for skipping test cases
Jacob Lifshay [Tue, 28 Jul 2020 23:49:10 +0000 (16:49 -0700)]
clean up div pipe tests to allow them to be run in parallel
Jacob Lifshay [Tue, 28 Jul 2020 23:16:45 +0000 (16:16 -0700)]
Merge remote-tracking branch 'origin/master'
Jacob Lifshay [Tue, 28 Jul 2020 23:15:40 +0000 (16:15 -0700)]
fix test_pipe_ilang.py
Luke Kenneth Casson Leighton [Tue, 28 Jul 2020 23:14:33 +0000 (00:14 +0100)]
use ctx.op compare (and muxid) in shiftrot proof
also use correct input record type and spec
Jacob Lifshay [Tue, 28 Jul 2020 23:02:20 +0000 (16:02 -0700)]
split out ilang tests
Jacob Lifshay [Tue, 28 Jul 2020 23:01:45 +0000 (16:01 -0700)]
add more files to .gitignore
Jacob Lifshay [Tue, 28 Jul 2020 22:49:06 +0000 (15:49 -0700)]
format code
Luke Kenneth Casson Leighton [Tue, 28 Jul 2020 12:28:22 +0000 (13:28 +0100)]
add preliminary investigative test of XICS ICS
Luke Kenneth Casson Leighton [Tue, 28 Jul 2020 09:20:20 +0000 (10:20 +0100)]
tidyup/comments in trap proof
Luke Kenneth Casson Leighton [Mon, 27 Jul 2020 21:36:55 +0000 (22:36 +0100)]
add 2nd part of XICS interrupt interface
Luke Kenneth Casson Leighton [Mon, 27 Jul 2020 11:44:44 +0000 (12:44 +0100)]
fix trap proof, and trap main_stage, and pseudocode for rfid
all a bit of a mess, really :)
Luke Kenneth Casson Leighton [Mon, 27 Jul 2020 10:48:11 +0000 (11:48 +0100)]
shorten expected_ to exp_, gets line-length down
Samuel A. Falvo II [Sun, 26 Jul 2020 20:31:17 +0000 (13:31 -0700)]
MTMSR(D) properties.
As of this commit, the properties for MTMSRD fails because (IBM) bit 30
is not set correctly. I've double checked my properties against that
specified in the V3.0B specs on page 978. I've also double-checked the
code in ../main_stage.py. As of this commit, I *cannot* find the
location of the discrepency.
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 20:27:53 +0000 (21:27 +0100)]
start on conversion of xics.vhdl to nmigen
see https://bugs.libre-soc.org/show_bug.cgi?id=407
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 13:47:17 +0000 (14:47 +0100)]
add nop test cases
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 13:16:15 +0000 (14:16 +0100)]
add test_nop general test case
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 13:13:31 +0000 (14:13 +0100)]
activate some of new accumulator-based tests in test_issuer
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 13:11:01 +0000 (14:11 +0100)]
do not need lod_l.q | lsto_l.q can just use lsd_l.q
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 13:04:54 +0000 (14:04 +0100)]
argh add yet another latch to detect when LD/ST has completed
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 12:34:49 +0000 (13:34 +0100)]
sigh, issue with detection/waiting for LD/ST CompUnit
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 11:13:36 +0000 (12:13 +0100)]
convert LDST test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 11:09:13 +0000 (12:09 +0100)]
convert Branch test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 11:07:28 +0000 (12:07 +0100)]
convert SPR test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 11:02:52 +0000 (12:02 +0100)]
convert TRAP test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:59:52 +0000 (11:59 +0100)]
remove FHDLTestCase
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:58:33 +0000 (11:58 +0100)]
convert CR test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:56:17 +0000 (11:56 +0100)]
convert mul test to accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:17:38 +0000 (11:17 +0100)]
convert shift_rot test to new base accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:14:18 +0000 (11:14 +0100)]
convert logical test case to new base class accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:11:25 +0000 (11:11 +0100)]
move run_test_program to base class and rename to "add_case"
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:11:05 +0000 (11:11 +0100)]
convert ALU to new accumulator style
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:05:34 +0000 (11:05 +0100)]
again, move large heavily-indented code-block in div test_pipe_caller
Luke Kenneth Casson Leighton [Sun, 26 Jul 2020 10:02:28 +0000 (11:02 +0100)]
run subtest, indentation getting too large, move to function