Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 09:16:54 +0000 (09:16 +0000)]
add test pspec for scoremulti to work
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 22:46:04 +0000 (22:46 +0000)]
convert hazard bitvectors to Reset-Priority SRLatch from nmutil
the read/write port were seriously getting in the way, by way of the
operand forwarding etc. etc. need instead to get either the immediate-latched
value (combinatorial) or the sync-delayed one, depending on circumstances.
Tobias Platen [Wed, 24 Nov 2021 18:50:05 +0000 (19:50 +0100)]
fix exception handling in pi_ld
Tobias Platen [Wed, 24 Nov 2021 18:30:44 +0000 (19:30 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 24 Nov 2021 18:30:25 +0000 (19:30 +0100)]
improve debug output in mmu.py
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 17:48:32 +0000 (17:48 +0000)]
fix write-after-write hazard detection
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 17:44:36 +0000 (17:44 +0000)]
when allow_overlap enabled do a manual wait until all FUs have
entirely finished befor going on to read the regfile state
this really should be done with the DMI interface, which needs updating
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:24:03 +0000 (16:24 +0000)]
code-comments
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:06:26 +0000 (16:06 +0000)]
add write-after-write hazard detection
stall if a WaW hazard is detected, continuing to assert the main decoder
so that the relevant bits of the write-vector can be read. these
bits are read *one clock behind* which is perfectly fine
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 15:18:08 +0000 (15:18 +0000)]
add 2nd hazard bitvector port for write-after-write
hazard detection
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 12:31:52 +0000 (12:31 +0000)]
whoops merged the two write-ports for RT and RA-with-update
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 11:55:14 +0000 (11:55 +0000)]
disable hazard vectors when overlap is not requested in core.py
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 22:45:03 +0000 (22:45 +0000)]
update submodules
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 22:44:55 +0000 (22:44 +0000)]
more comments
Tobias Platen [Tue, 23 Nov 2021 18:12:10 +0000 (19:12 +0100)]
pimem changes for st exception handling
Tobias Platen [Tue, 23 Nov 2021 17:42:22 +0000 (18:42 +0100)]
fix test_loadstore1.py
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 15:53:35 +0000 (15:53 +0000)]
add FU write-after-write hazard detection Signal (dummy so far)
this has to be set up in the connect_write section but then
*used* in connect_rdport in order to stop reading from happening
strictly speaking it should actually stop issue, but we already
established that that way lies madness (combinatorial loops).
this may turn out to be a bit more complex than initially planned
due to some instructions potentially not having read at all
(only write)
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 15:21:15 +0000 (15:21 +0000)]
add code-comments, link to in-order core
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 15:03:09 +0000 (15:03 +0000)]
more use of namedtuples in core.py for clarity
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 12:21:36 +0000 (12:21 +0000)]
start some use of namedtuples in core.py
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 12:11:49 +0000 (12:11 +0000)]
use some namedtuples to make things clearer in core.py
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 12:03:19 +0000 (12:03 +0000)]
use fascinating trick of defaultdict-of-defaultdicts
Tobias Platen [Mon, 22 Nov 2021 18:35:53 +0000 (19:35 +0100)]
add store testcase
Tobias Platen [Mon, 22 Nov 2021 17:57:54 +0000 (18:57 +0100)]
fix fast exception handling for pi_st
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 14:51:02 +0000 (14:51 +0000)]
make FetchFSM take PC as an input in its ispec
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 14:41:25 +0000 (14:41 +0000)]
local variable rename in FetchFSM
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 14:37:37 +0000 (14:37 +0000)]
split out FetchFSM into separate module
there are DriverConflicts which result in the FetchFSM being merged
into TestIssuerInternal but that is actually ok for now
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 11:59:19 +0000 (11:59 +0000)]
whoops accidentally committed commented-out test for overlap
in test_runner.py
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 22:57:35 +0000 (22:57 +0000)]
reset execute back to ISSUE_START if at INSN_WAIT and
stopping was requested.
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 22:44:42 +0000 (22:44 +0000)]
restrict (refine) hazard selection to the one being picked for this port
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 22:21:52 +0000 (22:21 +0000)]
block picker hazard on input to PriorityPicker rather than output
reason: another register could be picked if the input is blocked
but if the output is masked out, the picker will sit there with the
highest priority port stopping all others
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 21:12:14 +0000 (21:12 +0000)]
parse test_issuer args allow option "allow-overlap" to be optional
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 21:10:47 +0000 (21:10 +0000)]
complex. TestRunner now does not work properly unless recognising
that first, instructions can complete out-of-order from which they were
issued, and second, that just because the Function Unit has said it
accepted the instruction does not mean it has actually completed.
TestRunner therefore needed quite a bit of sorting out
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 21:09:09 +0000 (21:09 +0000)]
fixed issue with hazard dependencies, read will nott
take place until write dependencies are clear. currently extremely
draconian "ban" on entire FU progressing, actually probably all FUs
progressing, until write-hazards are clear. can sort out later
Tobias Platen [Sun, 21 Nov 2021 15:37:11 +0000 (16:37 +0100)]
add testcase for fast exceptions on store
Tobias Platen [Sat, 20 Nov 2021 15:16:37 +0000 (16:16 +0100)]
fix pi_ld testcase
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 19:20:13 +0000 (19:20 +0000)]
add both bitdict and selected args to connect_rd/wrport
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 17:56:23 +0000 (17:56 +0000)]
sorting out issue hazard conflicts in core.
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 17:41:25 +0000 (17:41 +0000)]
debug and cleanup
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 16:23:12 +0000 (16:23 +0000)]
rename instruction_active to instr_active in core
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 16:22:18 +0000 (16:22 +0000)]
read latch on regfile ports was fine, the combinatorial loop
is in the hazard detection on instruction issue
Tobias Platen [Fri, 19 Nov 2021 16:13:04 +0000 (17:13 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 15:33:58 +0000 (15:33 +0000)]
latch copy of read register numbers, not in use due to combinatorial loop
of some kind
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 14:49:41 +0000 (14:49 +0000)]
use read spec in connect_rdport rather than list of reads
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 14:47:54 +0000 (14:47 +0000)]
capture write regfile numbers into write latches in core
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 14:12:34 +0000 (14:12 +0000)]
code tidyup / comments, and use defaultdict
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 13:59:38 +0000 (13:59 +0000)]
create lists of latches in each FU, to record the read/write register
numbers required by the FU to read/write to regfiles.
previously, in the FSM-only version, these read/write regnums were
held (globally) by TestIssuer, and because only one instruction was
active, it did not matter.
now with the possibility of multiple instructions being run, it matters
(a lot)
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 13:22:05 +0000 (13:22 +0000)]
for some reason DMI CTRL returns status of 0x6 not 0x0
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 13:17:49 +0000 (13:17 +0000)]
missing argument, domain="sync" in JTAG instance
Luke Kenneth Casson Leighton [Fri, 19 Nov 2021 13:17:27 +0000 (13:17 +0000)]
return None if data returned is empty
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 23:19:32 +0000 (23:19 +0000)]
remove combinatorial loop in core instruction conflict detection
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 22:52:34 +0000 (22:52 +0000)]
experimenting with overlapping instructions, bit of a mess
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 22:08:00 +0000 (22:08 +0000)]
set up core processing FSM, which captures data if FU is not ready
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 21:40:48 +0000 (21:40 +0000)]
set up a temporary copy of CoreInput
(and fix CoreInput.eq, sigh)
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 21:24:19 +0000 (21:24 +0000)]
experiment allowing overlap (activated with --allow-overlap) in TestIssuer
Luke Kenneth Casson Leighton [Thu, 18 Nov 2021 13:25:29 +0000 (13:25 +0000)]
remove unneeded import
Tobias Platen [Thu, 18 Nov 2021 19:01:12 +0000 (20:01 +0100)]
more work on test_loadstore1
Jacob Lifshay [Wed, 17 Nov 2021 20:49:41 +0000 (12:49 -0800)]
start adding bitmanip FU
Tobias Platen [Wed, 17 Nov 2021 18:34:36 +0000 (19:34 +0100)]
PortInterfaceBase: fix fast exception handling
Tobias Platen [Wed, 17 Nov 2021 18:04:20 +0000 (19:04 +0100)]
whitespace
Tobias Platen [Wed, 17 Nov 2021 18:03:23 +0000 (19:03 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 17 Nov 2021 18:02:38 +0000 (19:02 +0100)]
fix mistake in test_pi2ls.py
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 18:01:27 +0000 (18:01 +0000)]
reading of regfile bitvector added, which activates on a per-FU basis
at the regfile read port
this is somewhat complete overkill because strictly speaking the
read should be done at issue time. fortunately, merging of lots of ORs
results in the exact same thing, just distributed
horribly inefficient though
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 17:42:05 +0000 (17:42 +0000)]
core hazard bitvector regfiles need to be readable
immediately (combinatorial) not via sync. allow synced option to
pass through from VirtualRegPort to RegFileArray
Tobias Platen [Wed, 17 Nov 2021 17:53:54 +0000 (18:53 +0100)]
fixed busy waiting in pi_st
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 16:23:45 +0000 (16:23 +0000)]
add option to test_issuer.py to allow for overlapping issue of
instructions. this is for Core hazard detection prior to moving to
an in-order core
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 16:15:37 +0000 (16:15 +0000)]
add ability to run hazard instruction for test purposes
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 14:44:40 +0000 (14:44 +0000)]
detect the case in Core bitvector when the Function Unit says:
"actually, although you said i *could* write to this regfile
(and therefore have been reserving a write hazard protection for me)
actually i'm not going to write to it."
this situation occurs when:
* at issue time a wrflag (from PowerDecoder decode_regspec_write) was HI
* at ALU output time (alu.n.o_ready) the FU dest.data.ok flag is LOW
under these unusual but perfectly valid circumstances the write hazard
bitvector MUST still be cleared
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 14:40:56 +0000 (14:40 +0000)]
add probe of whether CompUnit ALU is done or not.
this is used in core to detect whether the optional situation of
an ALU *maybe* writing to a regfile occurs or not
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 14:10:50 +0000 (14:10 +0000)]
missing optional check on make_hazard_vecs
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 14:08:50 +0000 (14:08 +0000)]
move core hazard set/clear to separate function, for clarity
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 13:40:08 +0000 (13:40 +0000)]
whoops context-indentation by mistake (no harm done, just odd)
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 13:34:52 +0000 (13:34 +0000)]
add a FetchOutput pipeline data structure
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 19:12:51 +0000 (19:12 +0000)]
print out regfile unary status, bit of name-cleanup
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 18:54:21 +0000 (18:54 +0000)]
use a virtual regfile port for the hazard bitvectors
this allows a full width of enables and full width of bits
(one per reg being written to)
Tobias Platen [Tue, 16 Nov 2021 18:22:53 +0000 (19:22 +0100)]
pi_ld busy waiting fix
Tobias Platen [Tue, 16 Nov 2021 17:24:59 +0000 (18:24 +0100)]
loadstore1 now reports exception reason
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 16:29:30 +0000 (16:29 +0000)]
create set/get ports for bitvectors
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 14:03:28 +0000 (14:03 +0000)]
capture write port (wrflag) in byregfiles_spec for use in
bitvector setting at issue time
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 13:36:26 +0000 (13:36 +0000)]
rename regports for bitvectors so that
* read regfile can SET the bitvector
* write regfile can CLEAR the bitvector
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 10:29:37 +0000 (10:29 +0000)]
starting to get write-clear of hazard vectors operating
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 10:28:46 +0000 (10:28 +0000)]
whoops, hazard vectors were depth 1 width N
they need to be regwidth 1 (1 bit wide) depth N (one per register)
Tobias Platen [Mon, 15 Nov 2021 19:29:13 +0000 (20:29 +0100)]
report dar on exception + test case
Tobias Platen [Mon, 15 Nov 2021 18:48:05 +0000 (19:48 +0100)]
add test_loadstore1.py
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 15:11:00 +0000 (15:11 +0000)]
add quick instructions on how to run pinouts.py to get some debug info
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 15:08:43 +0000 (15:08 +0000)]
update submodule to make ngi pointer router pinouts
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 15:07:23 +0000 (15:07 +0000)]
add new get_pinspec_resources function which creates nmigen
Resource/Subsignal/Pins suite from the JSON files generated by pinmux
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 14:42:05 +0000 (14:42 +0000)]
code-comment for get_pinspecs()
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 14:41:51 +0000 (14:41 +0000)]
start adding hazard vector setting in core (unfinished)
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 16:14:58 +0000 (16:14 +0000)]
debug prints
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 16:11:48 +0000 (16:11 +0000)]
fix regfile port names for "fast" port access (regreduce=False)
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 16:10:07 +0000 (16:10 +0000)]
TODO, implement is_dcbz
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 16:00:22 +0000 (16:00 +0000)]
code-comments
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 15:56:05 +0000 (15:56 +0000)]
split out core input/output into separate file core_data.py
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 15:51:39 +0000 (15:51 +0000)]
enable hazard vecs in core
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 14:56:09 +0000 (14:56 +0000)]
add exact same number - and name - bitvector ports to regfiles
for hazard purposes, easier to just have the exact same names
g
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 14:21:49 +0000 (14:21 +0000)]
code-morph regfile port specs to a dictionary format rather than hardcoded
this allows for Hazard Bit-vector regfiles to be created with exactly
the same regfile port names
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 10:29:19 +0000 (10:29 +0000)]
invert numbering on CR HDLState.get_crregs
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:42:53 +0000 (19:42 +0000)]
update store data reg 10 to 0xfe in virtmode mmu test
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:09:14 +0000 (19:09 +0000)]
remove read of MSR, it is done by passing through PowerDecoder2