Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 12:14:47 +0000 (12:14 +0000)]
in the middle of rewiring FPADD to use FPADDBase
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:09:15 +0000 (06:09 +0000)]
split out main stages of add to separate class, FPADDBase
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:08:20 +0000 (06:08 +0000)]
add function unit module
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:08:09 +0000 (06:08 +0000)]
correct syntax error
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 03:06:04 +0000 (03:06 +0000)]
add reservation station row module
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:50:36 +0000 (02:50 +0000)]
add MID testing
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:36:50 +0000 (02:36 +0000)]
add id to pack and putz
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:33:16 +0000 (02:33 +0000)]
add id to FPPack
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:30:20 +0000 (02:30 +0000)]
add id to FPCorrections
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:28:48 +0000 (02:28 +0000)]
add id to FPRound
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:26:13 +0000 (02:26 +0000)]
add id to norm1
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:24:54 +0000 (02:24 +0000)]
add id to stage1
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:22:19 +0000 (02:22 +0000)]
add id to stage0
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:18:39 +0000 (02:18 +0000)]
add id to align
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:15:21 +0000 (02:15 +0000)]
add id to denorm
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 00:58:31 +0000 (00:58 +0000)]
add id passthrough to specialcases class
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 23:41:18 +0000 (23:41 +0000)]
reorg special cases setup
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 23:38:19 +0000 (23:38 +0000)]
add id_width to parameters
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 10:59:07 +0000 (10:59 +0000)]
remove unneeded code
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 10:57:08 +0000 (10:57 +0000)]
reorg setup functions in more add phases
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 06:03:48 +0000 (06:03 +0000)]
cleanup modules, however multi-cycle align needs to be like norm1
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 05:39:06 +0000 (05:39 +0000)]
split out single-cycle normalisation to separate module
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 05:38:45 +0000 (05:38 +0000)]
enable single-cycle in FP16 test
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 04:25:56 +0000 (04:25 +0000)]
single-shift normalisation right-shift: normalisation now a single-cycle phase
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 04:13:02 +0000 (04:13 +0000)]
use MultiShiftRMerge module instead of shift_down_multi function
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:34:35 +0000 (02:34 +0000)]
remove chain dependence, calculate ediffs in parallel with comparisons
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:26:23 +0000 (02:26 +0000)]
comment out unneeded code for now
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:25:56 +0000 (02:25 +0000)]
convert to only use one multi-shifter
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 01:11:10 +0000 (01:11 +0000)]
rename stickybit variable
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 23:13:51 +0000 (23:13 +0000)]
unit test for multi-bit shift right with merge (sticky bit)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 10:12:51 +0000 (10:12 +0000)]
cleanup
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 10:12:04 +0000 (10:12 +0000)]
small optimisation, move subtraction of -126 from exponent into FPNumBase module, use it there and in normalisation
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:59:56 +0000 (09:59 +0000)]
add 3 extra unit tests
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:55:44 +0000 (09:55 +0000)]
limit count leading zeros to stop exponent shift-amount going below min exp
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:52:54 +0000 (09:52 +0000)]
fix shift class syntax errors (untested)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 02:34:20 +0000 (02:34 +0000)]
use priority encoder for normalisation in single cycle (done decrease)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 02:30:59 +0000 (02:30 +0000)]
add in FPNumShiftMultiRight class
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 19:20:25 +0000 (19:20 +0000)]
use bool() function instead of reduce(or_)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 18:02:20 +0000 (18:02 +0000)]
got single-cycle align working again (accidental combinatorial loop)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 14:13:45 +0000 (14:13 +0000)]
turn FPOp into module
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:58:45 +0000 (13:58 +0000)]
move put_z to PutZ class
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:14:28 +0000 (13:14 +0000)]
reorg pack setup
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:12:30 +0000 (13:12 +0000)]
reorg corrections setup
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:10:29 +0000 (13:10 +0000)]
remove unneeded function call
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:56:38 +0000 (12:56 +0000)]
remove global z as output from specialcases, use sc.out_z
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:47:46 +0000 (12:47 +0000)]
remove unneeded variable, use module overflow to get rounding signal
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:42:30 +0000 (12:42 +0000)]
managed to make round signal an output from normalisation phase
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:22:58 +0000 (11:22 +0000)]
tidyup, remove unneeded intermediate
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:22:26 +0000 (11:22 +0000)]
tidyup, remove unneeded intermediate
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:18:56 +0000 (11:18 +0000)]
reorg FPRound move setup function
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:16:05 +0000 (11:16 +0000)]
add comment about add0+add1 stages
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:09:44 +0000 (11:09 +0000)]
add1 module setup reorg
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:01:41 +0000 (11:01 +0000)]
remove temporary external z, use add0 output, connect as add1 input
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:52:52 +0000 (10:52 +0000)]
reorg: move add0 setup function
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:49:54 +0000 (10:49 +0000)]
use correct local output from pack chain
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:46:29 +0000 (10:46 +0000)]
reorganise normalisation init: move setup function from mod to class
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 04:00:38 +0000 (04:00 +0000)]
add module links (gives useful names)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 03:53:34 +0000 (03:53 +0000)]
complicated way to create a loop inside the normalisation module
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:47:31 +0000 (22:47 +0000)]
remove variable overflow
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:31:40 +0000 (22:31 +0000)]
connect corrections to pack without global z
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:25:40 +0000 (22:25 +0000)]
split roundz from norm z
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:14:02 +0000 (22:14 +0000)]
pass add0 z through to add1 independently
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 21:34:49 +0000 (21:34 +0000)]
add new temporary z for result chain
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 13:23:34 +0000 (13:23 +0000)]
connect add1 to norm1 overflow without global store
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 13:05:24 +0000 (13:05 +0000)]
merge normalise_1 and normalise_2 stages
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 12:01:26 +0000 (12:01 +0000)]
commennt use of intermediates
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 11:26:39 +0000 (11:26 +0000)]
store zero-extended a and b in temp signals
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 11:20:18 +0000 (11:20 +0000)]
store tests in temp signals
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 09:30:18 +0000 (09:30 +0000)]
experimenting with chaining Overflow module
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:15:53 +0000 (13:15 +0000)]
use output from align as input to add0
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:03:02 +0000 (13:03 +0000)]
remove commented-out code
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:02:18 +0000 (13:02 +0000)]
use GetOpMod for b
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 12:58:33 +0000 (12:58 +0000)]
create and use GetOp module
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 04:42:13 +0000 (04:42 +0000)]
move fpnum_b to class FPGetB
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 03:43:05 +0000 (03:43 +0000)]
narrowing down rounding error to use of Norm1 module
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 03:10:46 +0000 (03:10 +0000)]
separate denormalisation module and use it
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 02:48:45 +0000 (02:48 +0000)]
use denorm exponent signal
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 00:50:10 +0000 (00:50 +0000)]
sorting out unit tests, comply with IEEE754 on RISCV
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 00:13:05 +0000 (00:13 +0000)]
recompiled sfpy, testing FP16 again
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 23:09:06 +0000 (23:09 +0000)]
add Makefile patches to README
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:18:23 +0000 (17:18 +0000)]
whoops, overflow not right, reverting
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:14:21 +0000 (17:14 +0000)]
add failed test
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:14:17 +0000 (17:14 +0000)]
assign tests to signals
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:02:50 +0000 (17:02 +0000)]
create single and multi shift cycle, single doesnt work, multi does
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:34:32 +0000 (15:34 +0000)]
more chains between inputs and outputs
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:24:18 +0000 (15:24 +0000)]
move of = Overflow() out of FPADD, use chain
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:04:00 +0000 (15:04 +0000)]
remove tot from FPADD, use chain
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:58:51 +0000 (13:58 +0000)]
connect add0 to add1
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:56:31 +0000 (13:56 +0000)]
create add1 stage module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:30:36 +0000 (13:30 +0000)]
try some more chaining of inputs to outputs
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:21:22 +0000 (13:21 +0000)]
pass output from normalise_2 to input of roundz
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:15:01 +0000 (13:15 +0000)]
create add0 stage module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:31:15 +0000 (12:31 +0000)]
name modules correctly
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:29:32 +0000 (12:29 +0000)]
whoops norm2 using norm1 mod
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:26:16 +0000 (12:26 +0000)]
create normalise_2 module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:20:51 +0000 (12:20 +0000)]
put exponent > 126 logic in FPNumBase, use it in norm module
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:15:34 +0000 (12:15 +0000)]
split out first stage normalisation to module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 12:10:31 +0000 (12:10 +0000)]
reduce random case test numbers as well
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 11:47:15 +0000 (11:47 +0000)]
reduce number of unit test runs to get quicker more comprehensive coverage
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 11:46:54 +0000 (11:46 +0000)]
split special cases into separate module and use it