| 2021-05-07 |
Luke Kenneth Casson... | whoops, import error
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move LoadStore1 class to soc.fu.ldst.loadstore
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops was still copying output over in CommonOutputStage
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | how we managed to get this far without noticing that...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move dsisr and dar into LoadStore1
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move zero-dest-pred in Common Output Stage to not copy...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops setup of core.sv_pred_sm/dm not indented and...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | whoops disabled tests agaaaaain
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass relevant predicate mask bits through to Decoders...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | add in predicate mask bit detection when zeroing is...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass SVP64 ReMap field through to core and then on...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | moved exts* SVP64 unit tests to a different location
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | argh someobe falsely stated in the README that LibreSOC...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | if zeroing is set, put zero into input or output as...
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | simplify README.md so that it gets submitted to pypi
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | mark long description type as markdown
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | update NEWS.txt
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add libresoc-openpower-isa to setup.py dependencies
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | put sv_input_record_layout onto CompOpSubsetBase after all
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | whoops wrong signal name, set exc_happened
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add SVP64 RM fields to ALU input record
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove minerva debug unit (not needed)
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | minerva tests: Don't import soc.minerva.csr
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Silence pywriter harder
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Trim log output
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Fix invocation of pywriter
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build power-instruction-analyzer
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build c4m-jtag
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build openpower-isa
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Install Rust and cargo
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Remove tags from nmigen-soc repo
|
commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | whoops disabled some test_issuer group tests
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add SVSTATE (SVSRR0) to TRAP pipeline
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | adding fast3 SPR to Trap pipeline and unit test
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | new fast3 needs to be remapped to fast1 port in "reduced...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | missed that soc.regfile.util has moved to openpower...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add SVSRR0 to FastRegsEnum
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add TODO comments and cross-reference to bug
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | note a way to see if an exception happened, in TestIssuer
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add printout showing exception output from FUs
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove symlink
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add links in README
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | more rename of exception_o to exc_o, add convenience...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | wire in exc_o.happened into write-cancellation of LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | comments, and change name of LDSTCompUnit exception_o...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove exception from data on FUBaseData, explicitly...
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | code-comments for LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add LDSTException class to LDSTOutputData
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | add option to add exception type to FUBaseData (pipe_data)
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | rename IntegerData to FUBaseData
|
commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | comment out nc (nocache), it seems to actually work
|
commit | commitdiff | tree |
| 2021-05-03 |
Luke Kenneth Casson... | MMU: get store to activate only when data is available...
|
commit | commitdiff | tree |
| 2021-05-03 |
Luke Kenneth Casson... | disable the cache for now, whilst testing read/write...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | use Const to define bit-length when comparing top nibble...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | mmu FSM store in dcache: only put data onto d_in on...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | return d_out.valid instead of always "ok" in MMU FSM
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | HACK WARNING: disable d-cache on hard-coded address...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | add nc argument to dcache load/store tests
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | quick hack to SRAM test and to dcache to enable classic...
|
commit | commitdiff | tree |
| 2021-05-02 |
Luke Kenneth Casson... | adjust dependencies in setup.py
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | enable issuer_verilog.py to generate new MMU/DCache...
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | send a DMI RESET at the end of the test.
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | store data in microwatt dcache goes in one cycle AFTER...
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | dcache store test: data goes in one cycle AFTER valid...
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | only do dcache lookup for now
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | add LD/ST cases to MMU, which should all still work
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | add MMUTestCaseROM
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | use new AllFunctionUnits.get_fu function
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | use SPRreduced to match PowerDecoder2
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | missing self.
|
commit | commitdiff | tree |
| 2021-05-01 |
Luke Kenneth Casson... | resolve DriverConflict in TstL0CacheBuffer, really...
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | debug and stop on mmu test_pipe_caller.py
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | comments on dcache-to-mmu link
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | add a TestSRAM variant of LoadStore1, for being able...
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | add basic test_issuer_mmu.py
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | add option to use new mmu_cache_wb ConfigMemoryPortInterface
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | hook up dcache wb_in/out to PortInterfaceBase Wishbone...
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | sort out spblock 4k sram cell instance name to match...
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | https://bugs.libre-soc.org/show_bug.cgi?id=635
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | better reporting on gpr comparisons
|
commit | commitdiff | tree |
| 2021-04-30 |
Luke Kenneth Casson... | set up LoadStore1 in ConfigMemoryPortInterface and...
|
commit | commitdiff | tree |
| 2021-04-29 |
Luke Kenneth Casson... | comment out adding mmu and dcache to pspec in MMU FSM
|
commit | commitdiff | tree |
| 2021-04-29 |
Luke Kenneth Casson... | move dcache into Loadstore1
|
commit | commitdiff | tree |
| 2021-04-27 |
Luke Kenneth Casson... | add option to disable bus forwarding on SPRs and FAST...
|
commit | commitdiff | tree |
| 2021-04-27 |
Luke Kenneth Casson... | add option to enable/disable bus forwarding mode on...
|
commit | commitdiff | tree |
| 2021-04-27 |
Luke Kenneth Casson... | return read data out from Loadstore1 only when valid
|
commit | commitdiff | tree |
| 2021-04-26 |
Luke Kenneth Casson... | hook up MSR into MMU (TODO, use a lot less bits)
|
commit | commitdiff | tree |
| 2021-04-26 |
Luke Kenneth Casson... | simple regression dcache test was faulty. wishbone...
|
commit | commitdiff | tree |
| 2021-04-26 |
Luke Kenneth Casson... | comment read ack in sram
|
commit | commitdiff | tree |
| 2021-04-26 |
Luke Kenneth Casson... | incorrect indentation in dcache rams
|
commit | commitdiff | tree |
| 2021-04-26 |
Luke Kenneth Casson... | simplify dcache test
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | spelling mistake
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | remove RegStage1.real_adr temporary from dcache
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | do not overwrite parameter ra in dcache
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | comment out dcache_store from test, not the problem
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | remove unneeded code
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | read req in wb_in.stall, dcache
|
commit | commitdiff | tree |
| 2021-04-25 |
Luke Kenneth Casson... | add single regression test for dcache
|
commit | commitdiff | tree |
| next |
projects / soc.git / search