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Shift-out skipped mask bits for both crpred and intpred
2021-02-16
Cesar Strauss
Fix MSB0 issues for SVP64
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2021-02-15
Cesar Strauss
Simplify obtaining the PC from the register file
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2021-02-14
Cesar Strauss
Show traces for the register numbers of the current...
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2021-02-14
Cesar Strauss
Fix width of the "extra" input on the Extra decoder
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2021-02-14
Cesar Strauss
Fix conversion to MSB0
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2021-02-14
Cesar Strauss
Remove obsolete comment
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2021-02-13
Cesar Strauss
Fetch and decode the SVP64 prefix
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2021-02-13
Cesar Strauss
Check the PC value at the end of each instruction
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2021-02-13
Cesar Strauss
Skip vector test case, and add a scalar case
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2021-02-13
Cesar Strauss
Fix imports and whitespace
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2021-02-13
Cesar Strauss
Fix SVP64 translator to yield the unaltered instruction
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2021-02-06
Cesar Strauss
Fix whitespace
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2021-02-06
Cesar Strauss
Extract the fetch FSM out from the main FSM
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2021-02-01
Cesar Strauss
Add GTKWave document to test_issuer
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2021-01-31
Cesar Strauss
Fix loop test and enable it
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2021-01-01
Cesar Strauss
Add zero CR test case and fix comments
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2021-01-01
Cesar Strauss
Add test cases with rc=1
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2021-01-01
Cesar Strauss
Make all ports the same size, on the test ALU
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2021-01-01
Cesar Strauss
Add CR output port to test cases
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2021-01-01
Cesar Strauss
Add CR to the output data port
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2021-01-01
Cesar Strauss
Make output write enables independent of valid_o
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2021-01-01
Cesar Strauss
Move NOP test case earlier
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2021-01-01
Cesar Strauss
Disable data value output on NOP
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2021-01-01
Cesar Strauss
Add condition register (CR) output
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2020-12-31
Cesar Strauss
Implement and test NOP in the test ALU
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2020-12-31
Cesar Strauss
Don't use OP_NOP for zero-delay subtraction
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2020-12-31
Cesar Strauss
Test first input port being masked out
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2020-12-31
Cesar Strauss
Sign extend the second input port
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2020-12-31
Cesar Strauss
Test masked-out second input port
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2020-12-31
Cesar Strauss
Add sign extend to the Test ALU
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2020-12-31
Cesar Strauss
Show rdmaskn and wrmask in GTKWave
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2020-12-31
Cesar Strauss
Use the increment operator
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2020-12-31
Cesar Strauss
Add support for masked write operations
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2020-12-31
Cesar Strauss
Clarify reason for holding rdmaskn valid during the...
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2020-12-31
Cesar Strauss
Remove previous version of the CompUnit parallel unit...
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2020-12-31
Cesar Strauss
Only hold the decoder signals for one cycle, along...
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2020-12-30
Cesar Strauss
Test the rdmaskn control signal
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2020-12-29
Cesar Strauss
Remove left-over comments.
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2020-12-20
Cesar Strauss
Add support for CXXSim simulation
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2020-12-13
Cesar Strauss
Ignore formal verification output in the source directory
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2020-12-13
Cesar Strauss
Allow more test cases to be run with CXXSim
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2020-12-07
Cesar Strauss
Display the instruction type as a vector on cxxsim
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2020-12-06
Cesar Strauss
Whitespace
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2020-12-06
Cesar Strauss
Update GTKWave documents to work with latest cxxsim
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2020-12-05
Cesar Strauss
Write a GTKWave document to investigate why the proof...
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2020-12-05
Cesar Strauss
Use the DummyALU regspec and its corresponding OpSubset
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2020-11-28
Cesar Strauss
Fix signal names: go/rel -> go_i/rel_o
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2020-11-24
Cesar Strauss
Fix some typos and whitespace
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2020-11-24
Cesar Strauss
Port the DummyALU test case to the new parallel issuer
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2020-11-23
Cesar Strauss
Results are now a list, so "expected" should follow...
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2020-11-23
Cesar Strauss
Parameterize the issuer on the number of operands and...
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2020-11-22
Cesar Strauss
Refactor the ALU operation issuer into a class
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2020-11-22
Cesar Strauss
Port the ALU test case to the new parallel test style
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2020-11-22
Cesar Strauss
Add a GTKWave document to the ALU test case
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2020-11-19
Cesar Strauss
Separate input and output ports by color
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2020-11-19
Cesar Strauss
Explain the test cases
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2020-11-18
Cesar Strauss
Separate individual traces for each rel_o/go_i port
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2020-11-16
Cesar Strauss
Add a transaction counter to producers and consumers
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2020-11-15
Cesar Strauss
Implement ResultConsumer and port the Shifter unit...
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2020-11-14
Cesar Strauss
Move the DUT driver to within the test case process
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2020-11-14
Cesar Strauss
Fix and enable the regspec test for the Shifter
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2020-11-01
Cesar Strauss
Add a check for liveness.
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2020-10-31
Cesar Strauss
Check that the read and write counters differ at most...
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2020-10-31
Cesar Strauss
Remove stray comment
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2020-10-28
Cesar Strauss
Implement an operand producer that talks the rel_o...
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2020-10-24
Cesar Strauss
Create a GTKWave document for the test ALU unit tests
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2020-10-01
Cesar Strauss
Add GTKWave document to test_compunit_fsm
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2020-09-27
Cesar Strauss
Convert yet another few tests to be able to use latest...
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2020-09-26
Cesar Strauss
Convert a few more tests to be able to use cxxsim
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2020-09-24
Cesar Strauss
Use nmutil simulator module to simplify choosing among...
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2020-09-24
Cesar Strauss
Fix whitespace, remove unused imports
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2020-09-24
Cesar Strauss
Use nmutil simulator module to simplify choosing among...
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2020-09-22
Cesar Strauss
Port soc.experiment.alu_fsm to the new way of invoking...
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2020-09-20
Cesar Strauss
Add induction proof for the FSM Shifter
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2020-09-20
Cesar Strauss
Add bounded proof to FSM Shifter
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2020-09-20
Cesar Strauss
Let the formal engine create some test cases for the...
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2020-09-19
Cesar Strauss
Remove demonstration code
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2020-08-29
Cesar Strauss
Move new write_gtkw and its example to nmutil
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2020-08-23
Cesar Strauss
Allow an empty style, and passing default styles as...
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2020-08-23
Cesar Strauss
Add comment node type
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2020-08-23
Cesar Strauss
Add base and display styles
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2020-08-23
Cesar Strauss
Apply style from node own name
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2020-08-23
Cesar Strauss
Add color style
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2020-08-23
Cesar Strauss
Collect styles from the tuple
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2020-08-23
Cesar Strauss
Propagate the root style to all signals
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2020-08-22
Cesar Strauss
Move comments to the docstring
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2020-08-22
Cesar Strauss
Walk the DOM and emit the trace names
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2020-08-22
Cesar Strauss
First draft of a mini-language to describe GTKWave...
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2020-08-15
Cesar Strauss
Demonstrates string traces
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2020-08-15
Cesar Strauss
Demonstrates adding extra debug signals traces to the...
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2020-08-15
Cesar Strauss
Demonstrates creating stylish GTKWave "save" files...
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2020-07-20
Cesar Strauss
Document the move of sdir from data_i to op.
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2020-07-20
Cesar Strauss
Remove extra yield from test case.
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2020-07-19
Cesar Strauss
Implement control path and unit test.
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2020-07-18
Cesar Strauss
Implement the Shifter data path
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2020-07-18
Cesar Strauss
Document move of the next port data
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2020-07-09
Cesar Strauss
Define ports for a simple sequential Shifter
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2020-07-08
Cesar Strauss
Start the FSM-based ALU example.
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2020-07-07
Cesar Strauss
Clear input data along with valid_i
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2020-07-06
Cesar Strauss
Assert n.ready_i at the beginning of the cycle
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