| 2021-12-07 |
Luke Kenneth Casson... | complete the i-cache fetch through the MMU, including...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | set separate "iside" signal in LoadStore1 to not confuse it
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | start extending icache loadstore test
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | whoops another serious error in the CacheTagArray
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add first i-cache fetch (non-virtual), no MMU lookup...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add in I-Cache into LoadStore1 - presently unused ...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add discussion links and bugreport
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | invert mmureq statements
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | submodule tidyup
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | tidyup, comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | debug print
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | another major bug, CacheTagArray valid was only 1 bit...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | tidyup: move hit_set to DCachePendingHit in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | dcache.py tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | rename dtlb to dtlb_valid and tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert TLBArray to TLBValidArray
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert DTLBUpdate to use a pair of Memorys
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | update DTLBUpdate to reflect internal API now
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | ooo nasty bug. used tlb_hit.way instead of tlb_hit...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | move DTLB Tags/Valids/PTEs into DTLBUpdate module
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | start moving TLBArray into DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | PLRUs were selecting an output index, only one selected
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | repeated copies of read/write addr/sel to Cache SRAMs
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | move bank of PLRUs to their own submodule in both dcache...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use binary-to-unary encoders in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | global (one) do_read signal in cache_rams dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use one-hot binary-to-unary in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use i_in.req to gate hit_way via Decoder in icache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use Decoder (binary-to-unary) in icache.py to deal...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use unary encoding (one-hot) for replace_way hit_way...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace and minor cleanup of D-Cache
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | more use of TLBHit Record in D-Cache
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | correct tlb_hit_way and index sizes, use TLBHit Record...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use TLBRecord in D-Cache for which TLB is selected
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | split out TLBRecord, correct number of valid bits
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record in DCache for TLB
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record in D-Cache Cache Tags
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record for I-Cache Cache Tag/Valid
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record for ICache TLB
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | sorting out test_mmu_dcache.py to use wb_get
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | convert icache.py to standard wishbone Interface
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | fake up wishbone stall signal in icache.
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | fix icache row store issue
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | using same tag/row functions as in dcache.py
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | more signal sizes in icache.py
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | incorrect Signal sizes in icache.py,
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | sorting out icache.py, used to work
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | remove redundant code
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | add I-Cache standard bus (not used yet)
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | remove yet another duplicate copy of wb_get, possible...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | replace yet another duplicate copy of wb_get, possible...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | wishbone bus convert on dcache
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | correct import of wg_get function
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | remove yet another duplicated copy of wb_get and add...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | rename function which needs replacing
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | should have been using common version of wb_get, not...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | should not have been duplicating wb_get function in...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | get test_mmu_dcache.py working again
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | remove wb_get, should not have been duplicated
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | remove wb_get, should not have been massively duplicated...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | fix return results from pi_ld
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | wark-wark, broke mmu with removing rin. reverted
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | tidyup, comments
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | tidyup mmu
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | sigh in MMU FSM use direct access to ldst.dar/dsisr...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | remove DAR from PortInterface (where is the data going...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | stop using dar_o from PortInterface, get DAR directly...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | put DSISR and DAR publicly accessible in LoadStore1
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | whoops fix up exception happened if alignment triggers...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | fix pi_st which should not be trying to wait for the...
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | fixing DAR updating from exceptions
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | whoops
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | MMU lookup DSISR load bit inverted in LoadStore1
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | store DAR in LoadStore1
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | not busy if excrption occurs on MMU_LOOKUP in loadstore.py
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commit | commitdiff | tree |
| 2021-12-04 |
Luke Kenneth Casson... | add means to update dsisr from MMU FSM. TODO: add a...
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | priv_mode/virt_mode are set in the request, which is...
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | in loadstore.py set align_intr from request which comes...
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | driver conflict on priv_mode and virt_mode, do not...
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | fix up test_loadstore1.py
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | in loadstore.py, when an exception is done or if the FSM
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | fix PortInterfaceBase
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | fix up LDST test functions pi_ld and pi_st to respect...
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | add misaligned ld/st to trigger an exception
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commit | commitdiff | tree |
| 2021-12-03 |
Luke Kenneth Casson... | comment out dsisr and dar in mmu FSM for now
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commit | commitdiff | tree |
| 2021-12-02 |
Luke Kenneth Casson... | add a bitvector remap function, the plan is to use...
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commit | commitdiff | tree |
| 2021-12-02 |
Luke Kenneth Casson... | use new namedtuple in core when calling regspec_decode()
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commit | commitdiff | tree |
| 2021-12-02 |
Luke Kenneth Casson... | add module parameter to regspec_decode and therefore...
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commit | commitdiff | tree |
| 2021-12-01 |
Luke Kenneth Casson... | stack of changes to MultiCompUnit to speed it up
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commit | commitdiff | tree |
| 2021-12-01 |
Luke Kenneth Casson... | experimenting with option to shorten MultiCompUnit...
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commit | commitdiff | tree |
| 2021-12-01 |
Luke Kenneth Casson... | create single-stage ALU pipeline, shorten latency on...
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commit | commitdiff | tree |
| 2021-12-01 |
Luke Kenneth Casson... | allow MultiCompUnit to set read and write latches to...
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commit | commitdiff | tree |
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