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soc.git
2020-06-01
Luke Kenneth...
add test_bc_reg (fails)
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2020-06-01
Luke Kenneth...
remove unneeded fields from Decode2Execute1Type
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2020-06-01
Michael Nolan
Add proof for RegFile
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2020-06-01
Luke Kenneth...
more unneeded fields from SR InputRecord
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2020-06-01
Luke Kenneth...
remove data_len from SR input record
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2020-06-01
Luke Kenneth...
remove zero/invert from ShiftRot Input Record
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2020-06-01
Luke Kenneth...
add shift-rot input record and use it
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2020-06-01
Luke Kenneth...
CompBROpSubset exists
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2020-06-01
Luke Kenneth...
RS moved to port 1 (from port 3), remove need in ALU...
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2020-06-01
Michael Nolan
Add proof for RegFileArray
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2020-06-01
Luke Kenneth...
remove use of reg3 in logical pipeline: CSV files moved...
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2020-06-01
Michael Nolan
Have regfile use AnySeq instead of AnyConst
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2020-06-01
Luke Kenneth...
rotator carry is set into both XER CA and CA32 fields
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2020-06-01
Luke Kenneth...
comment out rlwinm. for now
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2020-06-01
Luke Kenneth...
argh - need to zero the src_i input after "Read" is...
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2020-06-01
Michael Nolan
Enable k-induction for register file proof
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2020-06-01
Michael Nolan
That was weird. For some reason it wasn't generating...
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2020-06-01
Michael Nolan
Full BMC proof of Register
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2020-06-01
Michael Nolan
Begin rewrite of proof_regfile.py
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2020-06-01
Luke Kenneth...
put RB in 2nd position (matching immediate) in ShiftRot...
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2020-06-01
Luke Kenneth...
sigh - another instance where write-mask needed to...
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2020-06-01
Luke Kenneth...
remove xer so/ov, swap rs/rb to correct(?) order in...
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2020-06-01
Tobias Platen
proof_datamerger wip
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2020-06-01
Luke Kenneth...
add rlwinm. test instruction (sets CR0)
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2020-06-01
Luke Kenneth...
remove duplicate signal
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2020-06-01
Luke Kenneth...
allow ALU / Logical ops to select RS as 1st operand
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2020-06-01
Luke Kenneth...
allow M*-Form shiftrot to swap RS/RB back to consistent...
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2020-06-01
Luke Kenneth...
add first version of ShiftRot CompUnit test
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2020-06-01
Luke Kenneth...
shiftrot uses LogicalOutputData not ALUOutputData
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2020-06-01
Cesar Strauss
Add rdmaskn parameter and assert it along issue_i
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2020-06-01
Luke Kenneth...
add assertions for branch compunit output
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2020-06-01
Luke Kenneth...
invert SPR1/2 in branch output data
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2020-06-01
Luke Kenneth...
decode SPRs for branch
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2020-06-01
Luke Kenneth...
swap over SPR1/2 to fit with microwatt SPR conventions
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2020-06-01
Luke Kenneth...
add first version compunit branch test
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2020-06-01
Luke Kenneth...
whoops need to read RS in CR inputs test
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2020-06-01
Luke Kenneth...
add first version of CR CompUnit test
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2020-06-01
Luke Kenneth...
minor adjustment, zero test in ALU output stage
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2020-06-01
Luke Kenneth...
remove unneeded code
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2020-05-31
Luke Kenneth...
bit-test on the function-unit value being tested
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2020-05-31
Luke Kenneth...
update isatables to cmpb not modifying CR0
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2020-05-31
Luke Kenneth...
add logical compunit test
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2020-05-31
Luke Kenneth...
comment inputs and outputs from ALU unit test
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2020-05-31
Luke Kenneth...
imports - use of globals. baaaad
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2020-05-31
Luke Kenneth...
remove unneeded code and inputs. convert to "naming...
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2020-05-31
Luke Kenneth...
split out common code from test_alu_compunit.py
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2020-05-31
Luke Kenneth...
add comments for MultiCompUnit parallel test
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2020-05-31
Luke Kenneth...
de-hard-code-ify getting results from MultiCompUnit
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2020-05-31
Luke Kenneth...
remove unneeded imports
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2020-05-31
Luke Kenneth...
split out compalu unit tests to separate module (gettin...
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2020-05-31
Luke Kenneth...
HA! found a bug in MultiCompUnit handling of write...
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2020-05-31
Luke Kenneth...
clarify
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2020-05-31
Luke Kenneth...
OP_CMPEQB also requesting change of output reg (stop...
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2020-05-31
Luke Kenneth...
OP_CMP is requesting a change of the output register...
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2020-05-31
Luke Kenneth...
still investigating
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2020-05-31
Luke Kenneth...
start with zero, try not to compare against 9 bytes...
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2020-05-31
Luke Kenneth...
more debug statements
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2020-05-31
Luke Kenneth...
add in more CR debug statements
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2020-05-31
Luke Kenneth...
copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
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2020-05-31
Luke Kenneth...
remove commented-out vars from ALU input record
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2020-05-31
Luke Kenneth...
write cr0 when op.write_cr.ok is set
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2020-05-31
Luke Kenneth...
add write_cr to ALU record subset
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2020-05-31
Luke Kenneth...
comment out xer ov/so for now
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2020-05-30
Luke Kenneth...
get carry from cr write_cr
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2020-05-30
Luke Kenneth...
select CR0 write out only when RC=1
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2020-05-30
Luke Kenneth...
set CR0 output when OP_CMP or OP_CMPEQB need it
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2020-05-30
Luke Kenneth...
add in use of "Settle"
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2020-05-30
Luke Kenneth...
add in write-mask into MultiCompUnit and MCU-ALU unit...
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2020-05-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-05-30
Tobias Platen
unit test for DataMerger
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2020-05-30
Luke Kenneth...
create read-mask for ALU CompUnit: switches off optiona...
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2020-05-30
Luke Kenneth...
create a write-mask, anything with an "ok" in the Recor...
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2020-05-30
Luke Kenneth...
allow MultiCompUnit outputs to be Records, to capture...
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2020-05-30
Luke Kenneth...
add read-mask to MultiCompUnit
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2020-05-30
Luke Kenneth...
code-shuffle / comments
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2020-05-30
Luke Kenneth...
mess - but a functional mess. ALU-MultiCompUnit semi...
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2020-05-30
Luke Kenneth...
grab other results from ALU pipeline in compunit test
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2020-05-30
Luke Kenneth...
order of XER so/ca wrong way round from regspec
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2020-05-30
Luke Kenneth...
still experimenting with ALU-CompUnit interaction
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2020-05-29
Luke Kenneth...
interesting. use of Settle() works, showing that Regfi...
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2020-05-29
Luke Kenneth...
module comments for popcount
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2020-05-29
Luke Kenneth...
comments on popcount
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2020-05-29
Luke Kenneth...
trigger ALU ready when operands ready
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2020-05-29
Tobias Platen
fixes for DataMerger
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2020-05-29
Luke Kenneth...
trigger read ALU ready/valid from latch as well
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2020-05-29
Luke Kenneth...
use a latch to communicate read/valid output from ALU
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2020-05-29
Tobias Platen
DataMerger: rename addr_match_i to addr_array_i
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2020-05-29
Tobias Platen
fixed 'return m is missing'
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2020-05-29
Tobias Platen
whitespace fixes
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2020-05-29
Luke Kenneth...
latch all output on ALU output valid
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2020-05-29
Luke Kenneth...
create read-done pulse
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2020-05-29
Luke Kenneth...
write-release moves out of "ALU valid" due to using...
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2020-05-29
Luke Kenneth...
signal start of request from when ALU triggers result...
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2020-05-29
Luke Kenneth...
create rising pulse from ALU valid
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2020-05-29
Luke Kenneth...
names of attributes needs to be dest_o not dest_i
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2020-05-29
Luke Kenneth...
rename output signals in Test ALU
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2020-05-29
Cesar Strauss
Allow immediate assertion of go in the same cycle as rel
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2020-05-29
Cesar Strauss
Correct typo
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2020-05-29
Cesar Strauss
Send a one-clock "go" pulse after a configurable number...
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2020-05-28
Luke Kenneth...
messing about with proof_regfile.py
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