soc.git
2020-08-17 Cole PoirierCreate file experiment/wb_types.py to mirror microwatt...
2020-08-17 Luke Kenneth... move Mask to nmutil
2020-08-17 Luke Kenneth... turn SelectableInt less/greater into signed versions.
2020-08-17 Luke Kenneth... use longer memtest in litex sim
2020-08-17 Luke Kenneth... adjust litex bios cmp test
2020-08-17 Luke Kenneth... fix signed variants of cmp in alu
2020-08-17 Luke Kenneth... add new cmp test for alu
2020-08-17 Luke Kenneth... use shift module in mmu. to be moved to nmutil
2020-08-16 Cole Poiriermmu.py fix formatting 80 char limit
2020-08-16 Luke Kenneth... attempting to track down bug in litex bios memtest
2020-08-16 Luke Kenneth... read delay on getting regfile data
2020-08-16 Luke Kenneth... limit debug reporting in litex sim to range of pc
2020-08-16 Luke Kenneth... cmp test from litex bios
2020-08-16 Luke Kenneth... remove vhdl comments
2020-08-16 Luke Kenneth... use simple one-line mask-generation
2020-08-16 Luke Kenneth... fix LD/ST pimem issue with rising_edge detection
2020-08-16 Luke Kenneth... missing vars, spelling corrections
2020-08-16 Luke Kenneth... big reorg, shuffle code to functions, makes the FSM...
2020-08-16 Luke Kenneth... spelling error, move perm_ok to local
2020-08-16 Luke Kenneth... more comment removal
2020-08-16 Luke Kenneth... more remove comments
2020-08-16 Luke Kenneth... removing more comments, tidyup
2020-08-16 Luke Kenneth... restore incorrect removal of zero-Cat at LHS (should...
2020-08-16 Luke Kenneth... continue tidyup, comment removal/review. use byte_reve...
2020-08-16 Luke Kenneth... fix batch of syntax errors found by running mmu.py
2020-08-16 Luke Kenneth... begin tidyup, removing comments after line-by-line...
2020-08-15 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-15 Cole Poiriermmu.py fix Cat() semantics fixes https://bugs.libre...
2020-08-15 Luke Kenneth... thanks to daveshah, added simulation of dram
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Luke Kenneth... rather big change to interaction between regfile and...
2020-08-15 Luke Kenneth... clear compalu data latch always on issue
2020-08-15 Cesar StraussDemonstrates string traces
2020-08-15 Cesar StraussDemonstrates adding extra debug signals traces to the...
2020-08-15 Cesar StraussDemonstrates creating stylish GTKWave "save" files...
2020-08-14 Luke Kenneth... remove latchregister, use sync to capture compunit...
2020-08-14 Luke Kenneth... ha! "state" (pc, msr) not properly passed to core
2020-08-14 Luke Kenneth... drop in insn_state synchronously in issuer, at same...
2020-08-14 Luke Kenneth... submodule update
2020-08-14 Luke Kenneth... hrfid unit test sets up HSRR0 and HSRR1
2020-08-14 Luke Kenneth... bad hack to get HSRR0/1 to be "same" as SRR0/1
2020-08-14 Luke Kenneth... bug in isa parser not recognising MSR as declared variable
2020-08-14 Luke Kenneth... hack to get hrfid not to alter msr 51
2020-08-14 Luke Kenneth... stop trying to read swap files
2020-08-14 Luke Kenneth... sync on alu results in compalu
2020-08-14 Luke Kenneth... update submodule, add hrfid
2020-08-14 Luke Kenneth... update submodule, add hrfid
2020-08-14 Luke Kenneth... finally, fix decoder combinatorial loop
2020-08-14 Luke Kenneth... fix test_compunit.py after moving decoder rdflags function
2020-08-14 Luke Kenneth... add hrfid unit test
2020-08-14 Luke Kenneth... sync up the core decode-execute state,
2020-08-14 Luke Kenneth... move instruction decoder out of core
2020-08-14 Luke Kenneth... move regspec / rdflag decoding functions out of PowerDe...
2020-08-14 Luke Kenneth... sort out instruction stop/cancel when adding a new...
2020-08-14 Luke Kenneth... put multi-ports back (for read) on int and fast regfiles
2020-08-14 Luke Kenneth... reduce decoder pathways when exception occurs
2020-08-14 Luke Kenneth... divide shiftrot pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide alu pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide logical pipe into 2 (simple phase last)
2020-08-14 Jacob Lifshayrunning the simulator works!
2020-08-13 Jacob Lifshayadd --cpu=libresoc to Makefile
2020-08-13 Luke Kenneth... fix dmi reg read
2020-08-13 Luke Kenneth... code-shuffle
2020-08-13 Luke Kenneth... remove use of latchregigister, replace with sync on...
2020-08-13 Luke Kenneth... sync on pc writing when changed
2020-08-13 Cole Poirierdcache.py add initial imports
2020-08-13 Cole Poiriermem_types.py add more types from common.vhdl
2020-08-13 Cole Poiriermove memory related types from mmu.py into new file...
2020-08-13 Luke Kenneth... sync on reset in compalu
2020-08-13 Luke Kenneth... add forwarding-bus mode to Regfile Memory (and disable it)
2020-08-13 Luke Kenneth... sync on port interface address in ld/st compunit, and...
2020-08-13 Luke Kenneth... another sync to cut latency
2020-08-13 Cole PoirierInitial commit of translation of microwatt dcache.vhdl...
2020-08-13 Luke Kenneth... remove latchregister, sync src oper_i into MultiCompUnit
2020-08-13 Luke Kenneth... minor tidyup on alu compunit:
2020-08-13 Luke Kenneth... plenty of time to wait for operand, so use "sync" in...
2020-08-13 Luke Kenneth... sigh. convert Fast regfile to binary
2020-08-13 Luke Kenneth... sync on read of regfile ports
2020-08-13 Luke Kenneth... sigh. convert INT regfile to binary addressing
2020-08-13 Luke Kenneth... create a RegFileMem class that uses Memory
2020-08-12 Jacob Lifshayadd run_sim to Makefile
2020-08-12 Cole Poiriermmu.py add skeleton sim and test functions from regfile...
2020-08-12 Cole PoirierDelete unnecessary mmu dir, move mmu.py out of mmu...
2020-08-12 Cole PoirierRevert "Remove mmu dir and associated mmu/test/ dir...
2020-08-12 Cole PoirierRemove mmu dir and associated mmu/test/ dir
2020-08-12 Cole PoirierRemove rst signals, fix len of hex Consts, fix variable...
2020-08-12 Cole PoirierCreate dir experiment/mmu then mmu/test with skeleton...
2020-08-12 Cole Poiriermmu.py add RecordObject classes from common.vhdl input...
2020-08-12 Cole Poiriermmu.py remove TODOs for vhdl (others => '0') as they...
2020-08-12 Cole Poiriermmu.py fix or(block of logic) to be (block of logic...
2020-08-12 Cole Poiriermmu.py fix length of hex const https://bugs.libre-soc...
2020-08-12 Cole Poiriermmu.py remove class AddrShifter
2020-08-12 Cole PoirierFix typo in mmu.py
2020-08-11 Cole Poiriermmu.py fix formatting, use Cat() where '&' in mmu.vhdl
2020-08-11 Tobias Plateninitial version of L0CacheBuffer2
2020-08-11 Luke Kenneth... sigh, remove yet another int regfile read port
2020-08-11 Luke Kenneth... massive reduction in gate count by using alternative...
2020-08-11 Luke Kenneth... reduce regfile port usage for INT and FAST
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