| 2022-04-03 |
Cesar Strauss | Implement a debug port on the pseudo 1W/1R SRAM |
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| 2022-04-03 |
Cesar Strauss | Formal proof of the phased write dual port memory wrapper |
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| 2022-04-03 |
Luke Kenneth... | correct default to zero string not zero int |
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| 2022-04-03 |
Luke Kenneth... | add alternative pc_reset argument to issuer_verilog.py |
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| 2022-04-03 |
Luke Kenneth... | fix some of instantiation errors in opencores_ethmac.py |
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| 2022-04-02 |
Raptor Engineering... | Fix opencores EthMAC module wiring |
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| 2022-04-02 |
Cesar Strauss | Implement transparent read ports on the phased write... |
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| 2022-04-02 |
Cesar Strauss | Implement and test a "phased write port" memory |
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| 2022-03-31 |
Luke Kenneth... | invert cs_n pin in Tercel |
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| 2022-03-30 |
Luke Kenneth... | nope, default features in Tercel WB Buses need to not... |
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| 2022-03-29 |
Luke Kenneth... | add bus.err to list of default Wishbone signals in... |
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| 2022-03-29 |
Luke Kenneth... | byte-reverse Tercel read/write data and config bus... |
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| 2022-03-29 |
Luke Kenneth... | set clock freq Constant length to 32-bit in Tercel. |
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| 2022-03-29 |
Luke Kenneth... | self.specials does not exist, Instances must be added... |
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| 2022-03-29 |
Luke Kenneth... | more sorting out wishbone names in Tercel |
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| 2022-03-29 |
Luke Kenneth... | fix names of Instance signals in Tercel |
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| 2022-03-29 |
Luke Kenneth... | sort out variable names in Tercel |
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| 2022-03-29 |
Luke Kenneth... | self.comb does not exist, comb is a local temp-var... |
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| 2022-03-29 |
Luke Kenneth... | whitespace cleanup (80 char limit) |
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| 2022-03-29 |
Raptor Engineering... | Add initial integration for OpenCores 10/100 Ethernet MAC |
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| 2022-03-27 |
Cesar Strauss | Finish the SRAM formal proof by implementing induction |
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| 2022-03-26 |
Cesar Strauss | Add formal verification of the single port memory block |
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| 2022-03-26 |
Luke Kenneth... | rename PLRU modules to avoid conflict in microwatt |
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| 2022-03-18 |
Luke Kenneth... | whitespace cleanup (80 char limit, pep8) |
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| 2022-03-18 |
Luke Kenneth... | turn CompALU/CompLDST latches synchronous |
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| 2022-03-16 |
Raptor Engineering... | Add initial Tercel integration |
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| 2022-03-13 |
Cesar Strauss | Simulate some read/write/modify operations on the SRAM... |
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| 2022-03-13 |
Cesar Strauss | Add a Single R/W Port SRAM model |
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| 2022-03-12 |
Luke Kenneth... | add extra pipeline stages to ALU FU to make timing |
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| 2022-03-12 |
Luke Kenneth... | introduce extra register of delay to split combinatoria... |
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| 2022-03-12 |
Luke Kenneth... | Revert "read last row from r.wb.adr not r.req_adr in... |
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| 2022-03-12 |
Luke Kenneth... | Revert "store cur_state.pc+4 in separate register to... |
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| 2022-03-12 |
Luke Kenneth... | store cur_state.pc+4 in separate register to help reduce |
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| 2022-03-12 |
Luke Kenneth... | read last row from r.wb.adr not r.req_adr in icache |
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| 2022-03-08 |
Luke Kenneth... | remove stbs_done in icache.py |
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| 2022-03-08 |
Luke Kenneth... | remove ld_stbs_done from dcache: not needed |
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| 2022-03-08 |
Luke Kenneth... | work-in-progress on sdram opencores wrapper |
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| 2022-03-06 |
Cesar Strauss | Copy the startup delay from issuer.py to inorder.py |
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| 2022-02-28 |
Luke Kenneth... | attempting to introduce an extra few clock cycles delay... |
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| 2022-02-27 |
Luke Kenneth... | for lulz make I-Cache possible to set to 32-bit (XLEN=32) |
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| 2022-02-27 |
Luke Kenneth... | bit_length is 1 more than needed: subtract 1 from XLEN... |
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| 2022-02-27 |
Luke Kenneth... | fix up shift_rot test_pipe_caller to new regspeckls... |
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| 2022-02-27 |
Luke Kenneth... | convert shift_rot pipeline to XLEN=32/64 |
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| 2022-02-27 |
Luke Kenneth... | fix up Logical pipeline to produce HDL with XLEN=32 |
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| 2022-02-27 |
Luke Kenneth... | whoops ALU common output target must be XLEN-bit, |
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| 2022-02-27 |
Luke Kenneth... | set up dummy parent_pspec to pass XLEN=64 in |
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| 2022-02-27 |
Luke Kenneth... | start on converting MUL and DIV pipelines to XLEN |
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| 2022-02-27 |
Luke Kenneth... | convert from public static functions/properties for... |
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| 2022-02-27 |
Luke Kenneth... | fix ALU with XLEN=32, carry and overflow |
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| 2022-02-27 |
Luke Kenneth... | use XLEN in Function Units (starting with ALU) |
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| 2022-02-27 |
Luke Kenneth... | add XLEN to issuer_verilog.py defaults to 64 |
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| 2022-02-27 |
Luke Kenneth... | add XLEN option to regfiles via pspec |
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| 2022-02-24 |
Jacob Lifshay | add running instructions |
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| 2022-02-24 |
Jacob Lifshay | add formal proof for shift/rot o.ok |
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| 2022-02-24 |
Jacob Lifshay | clean up code |
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| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCR |
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| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCL |
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| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLC |
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| 2022-02-23 |
Luke Kenneth... | forgot to pass cix (cache-inhibited) through to LD... |
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| 2022-02-22 |
Jacob Lifshay | speed up shift/rot formal proof by running stuff in... |
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| 2022-02-21 |
Luke Kenneth... | again reduce combinatorial chains, similar to Trap... |
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| 2022-02-20 |
Luke Kenneth... | add syn_ramstyle "block_ram" attributes and reduce... |
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| 2022-02-20 |
Luke Kenneth... | same as shiftrot, split out separate pipelines for... |
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| 2022-02-20 |
Luke Kenneth... | put LDST go-store on a 1-clock delay to help with combi... |
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| 2022-02-20 |
Luke Kenneth... | name core_stop and terminated_o synchronous to potentia... |
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| 2022-02-20 |
Luke Kenneth... | nope, it's perfectly fine |
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| 2022-02-20 |
Luke Kenneth... | weird exception, oe not found in the shiftrot input... |
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| 2022-02-20 |
Luke Kenneth... | separate out shiftrot stages due to size of main stage... |
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| 2022-02-18 |
Luke Kenneth... | add blockram style to regfile Memory |
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| 2022-02-18 |
Luke Kenneth... | use block_ram attribute for FPGA synthesis |
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| 2022-02-18 |
Luke Kenneth... | reduce number of d-cache lines in microwatt fpga mode |
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| 2022-02-18 |
Luke Kenneth... | couple of adjustments to reduce gate count in i/d-cache |
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| 2022-02-18 |
Luke Kenneth... | add SDRAM Configuration Record |
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| 2022-02-18 |
Luke Kenneth... | reduce TLB set size from 64 to 16 to get FPGA resource... |
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| 2022-02-18 |
Luke Kenneth... | drastically reduce I-Cache size in microwatt-compat... |
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| 2022-02-18 |
Luke Kenneth... | parameterise I-Cache similar to D-Cache. lots of "self." |
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| 2022-02-18 |
Jacob Lifshay | add grev |
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| 2022-02-17 |
Luke Kenneth... | add opencores SDRAM verilog wrapper |
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| 2022-02-16 |
Luke Kenneth... | oof. big update to DCache to accept config parameters |
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| 2022-02-16 |
Luke Kenneth... | connect UART16550 pins if given |
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| 2022-02-15 |
Luke Kenneth... | for *write* the counter-address on downconvert was... |
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| 2022-02-15 |
Luke Kenneth... | add wishbone downconvert "skip" of slave sel so that... |
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| 2022-02-15 |
Luke Kenneth... | add SysCon reg_info, has uart and has large SYSCON |
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| 2022-02-15 |
Luke Kenneth... | sigh, stall was not working but actually turns out... |
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| 2022-02-15 |
Luke Kenneth... | add option to specify UART16550 width (32/8) |
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| 2022-02-15 |
Luke Kenneth... | add beginnings of syscon bus peripheral |
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| 2022-02-15 |
Luke Kenneth... | update comments |
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| 2022-02-15 |
Luke Kenneth... | resolve WBDownConvert ack issues when stall is active |
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| 2022-02-14 |
Luke Kenneth... | strip first 3 bits of WB address from microwatt d/i... |
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| 2022-02-14 |
Luke Kenneth... | slave sends stall signal, master receives, in |
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| 2022-02-14 |
Luke Kenneth... | sort out ExternalCore signal names |
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| 2022-02-14 |
Luke Kenneth... | add wishbone slave signal to downconvert if present |
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| 2022-02-14 |
Luke Kenneth... | add external core verilog wrapper, ironically around... |
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| 2022-02-13 |
Luke Kenneth... | bugfixing for ls2 imports of uart16550 |
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| 2022-02-13 |
Luke Kenneth... | Revert "remove dummy trap pipeline" |
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| 2022-02-13 |
Luke Kenneth... | Revert "doh" |
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| 2022-02-10 |
Andrey Miroshnikov | Added optional reverse arg to send TDI data MSB-first |
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| 2022-02-09 |
Luke Kenneth... | add opencores uart16550 instance wrapper |
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| 2022-02-01 |
Tobias Platen | correct path for make target microwatt_external_core |
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| 2022-01-31 |
Luke Kenneth... | fix bug in itlb_valid SRLatch set/reset, a bit weird... |
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