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litex.git
2020-08-06
sadullah
update BlackParrot transducer
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2020-08-06
sadullah
Blackparrot human name update
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2020-08-06
enjoy-digital
Merge pull request #623 from Dolu1990/vexriscv_smp
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2020-08-06
Dolu1990
cpu/vexriscv_smp Add --with-coherent-dma
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2020-08-05
Florent Kermarrec
integration/soc/add_sdram: update rules to connect...
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2020-08-05
Florent Kermarrec
cpu/vexriscv_smp: fix args_read.
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2020-08-05
Florent Kermarrec
cpu/vexriscv_smp: cleanup, fix coherent_dma connection.
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2020-08-05
enjoy-digital
Merge pull request #622 from antmicro/fix_connectors
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2020-08-05
Florent Kermarrec
soc/interconnect/axi: minor cleanups.
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2020-08-05
Florent Kermarrec
interconnect/stream: set default AsyncFIFO depth to...
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2020-08-05
Pawel Sagan
arty: Change USB-uart and I2S Pmod configuration
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2020-08-05
Florent Kermarrec
interconnect/csr: add CSR registers ordering support.
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2020-08-05
Florent Kermarrec
soc/interconnect/csr: improve ident.
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2020-08-04
Florent Kermarrec
integration/soc: add expection on decoder when full...
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2020-08-04
Florent Kermarrec
wishbone: revert default adr_width to 30.
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2020-08-04
Florent Kermarrec
tools/litex_json2dts: add missing copyrights.
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2020-08-04
Florent Kermarrec
setup: add litex_json2dts to console_scripts.
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2020-08-04
enjoy-digital
Merge pull request #620 from antmicro/add_litex_json2dts
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2020-08-04
Florent Kermarrec
build/sim/config: add default_clk/default_clk_freq...
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2020-08-04
Florent Kermarrec
build/sim: use json_object_get_int64 instead of json_ob...
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2020-08-04
enjoy-digital
Merge pull request #619 from antmicro/jboc/sim-clocker
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2020-08-04
Mateusz Holenko
json2dts: Add Linux DT generation script
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2020-08-04
Jędrzej Boczar
build/sim: improve timebase calculation (strict checks...
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2020-08-04
Florent Kermarrec
cores/uart: add txempty/rxfull CSRs.
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2020-08-04
Florent Kermarrec
tools/litex_server: enable read_merger with CommUDP.
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2020-08-04
Florent Kermarrec
test: specify wishbone adr_width on AXI(Lite)<-->Wishbo...
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2020-08-04
enjoy-digital
Merge pull request #617 from gsomlo/gls_rocket_dma
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2020-08-03
Gabriel Somlo
debug: make CI print offending values
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2020-08-03
Gabriel Somlo
liblitesdcard/sdcard: (temporarily) slow down SDCARD_CL...
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2020-08-03
Gabriel Somlo
cores/cpu/rocket: expose slave port for DMA
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2020-08-03
Gabriel Somlo
integration/soc: make DMA slave region cover (at least...
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2020-08-03
Gabriel Somlo
interconnect/wishbone: increase WB address width to 31
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2020-08-03
Gabriel Somlo
soc/interconnect/axi: add Wishbone2AXI converter
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2020-08-03
Florent Kermarrec
cores/gpio: add support for Record on GPIOOut, GPIOIn...
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2020-08-03
Jędrzej Boczar
build/sim: allow for arbitrary clocks generation using...
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2020-08-03
Jędrzej Boczar
build/sim: use a real timebase in the simulation
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2020-08-03
enjoy-digital
Merge pull request #615 from pepijndevos/openfpgaloader
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2020-08-01
Pepijn de Vos
remove debugging
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2020-08-01
Pepijn de Vos
add openFPGAloader programmer
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2020-07-31
Florent Kermarrec
cpu/vexriscv/core: use variant name as human_name.
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2020-07-31
Florent Kermarrec
cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache...
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2020-07-30
Florent Kermarrec
cpu/zynq7000: set csr map to 0x00000000.
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2020-07-30
enjoy-digital
Merge pull request #611 from antmicro/jboc/axi-lite
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2020-07-30
Florent Kermarrec
tools/litex_server/read_merger: review/simplify a bit.
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2020-07-30
enjoy-digital
Merge pull request #605 from cklarhorst/feature-uart...
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2020-07-30
Jędrzej Boczar
soc/interconnect/axi: add AXILite -> AXI converter
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2020-07-30
Florent Kermarrec
cpu/blackparrot: minor cleanups, add sim variant (since...
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2020-07-29
enjoy-digital
Merge pull request #610 from Dolu1990/vexriscv_smp
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2020-07-29
Dolu1990
soc/cores/cpu/vexriscv_smp enable dynamic litedram...
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2020-07-29
Dolu1990
Merge branch 'master' into vexriscv_smp
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2020-07-29
Florent Kermarrec
integration/soc/add_sdram: allow the CPU to add the...
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2020-07-29
Florent Kermarrec
cores/cpu/rocket: add use_memory_bus parameter to easil...
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2020-07-28
Dolu1990
Merge branch 'master' into vexriscv_smp
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2020-07-28
Dolu1990
soc/cores/cpu/vexriscv_smp config update
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2020-07-28
Florent Kermarrec
CHANGES: update.
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2020-07-28
Florent Kermarrec
cpu/vexriscv_smp: move litedram import, remove os.path...
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2020-07-28
Florent Kermarrec
litex_setup: fix vexriscv-smp repository.
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2020-07-28
enjoy-digital
Merge pull request #607 from Dolu1990/vexriscv_smp
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2020-07-28
Dolu1990
soc/cores/cpu/vexriscv_smp integration
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2020-07-28
Florent Kermarrec
liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
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2020-07-27
Florent Kermarrec
integration/soc/etherbone: expose ethcore (useful to...
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2020-07-27
Florent Kermarrec
integration/soc: fix dma_bus typo.
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2020-07-26
Christian Klarhorst
Merge sequential reads for the UART litex_server backend
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2020-07-24
Florent Kermarrec
targets: keep in sync with litex-boards.
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2020-07-24
enjoy-digital
Merge pull request #604 from antmicro/jboc/axi-lite
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2020-07-24
Jędrzej Boczar
soc/interconnect/axi: add basic AXI Lite up-converter
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2020-07-24
Sean Cross
Merge pull request #603 from enjoy-digital/socdoc-exten...
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2020-07-24
Sean Cross
doc: socdoc: document new `sphinx_extra_config` parameter
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2020-07-24
enjoy-digital
Merge pull request #602 from enjoy-digital/socdoc-exten...
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2020-07-24
Sean Cross
litex: add `sphinx_extra_config` to `generate_docs()`
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2020-07-24
Sean Cross
doc: socdoc: document `sphinx_extensions` parameter
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2020-07-24
Jędrzej Boczar
soc/interconnect/axi: separate AXI Lite converter channels
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2020-07-23
Florent Kermarrec
CHANGES: update.
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2020-07-23
Florent Kermarrec
core/cpu: integrate Zynq as a classical CPU (Zynq7000...
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2020-07-22
Florent Kermarrec
liblitesdcard/sdcard: use max divider of 256 (128 was...
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2020-07-22
Florent Kermarrec
CHANGES: update.
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2020-07-22
enjoy-digital
Merge pull request #600 from antmicro/jboc/axi-lite
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2020-07-22
Florent Kermarrec
soc: add initial DMA bus support (optionally provided...
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2020-07-22
Jędrzej Boczar
test/axi: move all AXI Lite tests to separate file
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2020-07-22
Jędrzej Boczar
soc/integration: use AXILiteSRAM when using bus_standar...
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2020-07-22
Jędrzej Boczar
test/axi: add crossbar stress tests
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2020-07-22
Jędrzej Boczar
soc/integration: add bus standard parser arguments
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2020-07-22
Jędrzej Boczar
soc/interconnect/axi: improve Timeout module and test...
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2020-07-22
Jędrzej Boczar
test/axi: add shared AXI Lite interconnect tests
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2020-07-22
Jędrzej Boczar
soc/interconnect/axi: implement AXI Lite decoder
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2020-07-22
Jędrzej Boczar
soc/interconnect/axi: lock AXILiteArbiter until all...
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2020-07-22
Jędrzej Boczar
test/test_axi: add AXI Lite interconnect arbiter tests
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2020-07-22
Jędrzej Boczar
socinterconnect/axi: interconnect shared sketch
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2020-07-22
Jędrzej Boczar
soc/interconnect/axi: point-to-point interconnect and...
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2020-07-22
Jędrzej Boczar
soc/integration: choose interconnect based on bus standard
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2020-07-22
Jędrzej Boczar
soc/integration: add axi-lite standard to SoCBusHandler
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2020-07-22
enjoy-digital
Merge pull request #599 from antmicro/gen-mmcm-pr
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2020-07-22
Piotr Binkowski
litex-gen: add mmcm core
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2020-07-22
Florent Kermarrec
boards: keep in sync with litex-boards.
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2020-07-21
Florent Kermarrec
soc/integration/add_sdcard: add direct connection to...
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2020-07-21
Florent Kermarrec
cpu/vexriscv/system.h: update flush_cpu_dcache.
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2020-07-21
Florent Kermarrec
interconnect/wishbone: add minimal UpConverter.
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2020-07-20
enjoy-digital
Merge pull request #597 from antmicro/jboc/litex-builde...
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2020-07-20
enjoy-digital
Merge pull request #595 from betrusted-io/master
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2020-07-20
enjoy-digital
Merge pull request #598 from sergachev/master
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