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soc.git
2020-07-19
Luke Kenneth...
update to expose signals at top-level of issuer
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2020-07-19
Luke Kenneth...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth...
use same write_vcd for cxxsim as pysim
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2020-07-19
Luke Kenneth...
fix bug in alu_fsm.py found by cxxsim: missing one...
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2020-07-19
Luke Kenneth...
add some CompUnit demo tests of the alu_fsm example
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2020-07-19
Luke Kenneth...
move sdir to CompFSMOpSubset in alu_fsm example
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2020-07-19
Luke Kenneth...
add CompFSMOpSubset, also change dir to sdir
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2020-07-19
Luke Kenneth...
remove unneeded import
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2020-07-19
Luke Kenneth...
if nmigen.sim.pysim import fails use nmigen.back.pysim
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2020-07-19
Luke Kenneth...
use iocontrol PrevControl / NextControl instead of...
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2020-07-19
Luke Kenneth...
add DivTestCase to test_issuer.py (commented out for...
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2020-07-19
Cesar Strauss
Implement control path and unit test.
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2020-07-18
Luke Kenneth...
worked out that DivPipeSpec can be given a default...
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2020-07-18
Luke Kenneth...
missing conversion of DIV to Div
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2020-07-18
Luke Kenneth...
add option to generate verilog
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2020-07-18
Luke Kenneth...
whoops use slice not range
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2020-07-18
Luke Kenneth...
syntax error
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2020-07-18
Cesar Strauss
Implement the Shifter data path
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2020-07-18
Cesar Strauss
Document move of the next port data
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2020-07-18
Luke Kenneth...
add SR latch cxxrtl backend demo
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2020-07-18
Luke Kenneth...
add comment and copy of pseudo-code for OP_RFID into...
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2020-07-18
Luke Kenneth...
review of OP_RFID showed up some errors
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2020-07-18
Luke Kenneth...
corrections to trap main_stage.py OP_RFID according...
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2020-07-18
Samuel A. Falvo II
WIP: FV failing for unknown reasons.
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2020-07-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-18
Jacob Lifshay
add div fsm core (`DivState*`) with tests
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2020-07-18
Samuel A. Falvo II
Failing test: fast1/fast2 vs srr0/srr1? on trap pipe
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2020-07-18
Samuel A. Falvo II
forgot to clean up workspace in source
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2020-07-18
Samuel A. Falvo II
FV props for SC instruction
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2020-07-17
Samuel A. Falvo II
First FV property for trap unit
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Jacob Lifshay
start adding FSMDivCore*
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2020-07-17
Luke Kenneth...
comment explaining why not to call self.trap in PowerDe...
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2020-07-17
Luke Kenneth...
likewise cut across latest Minerva loadstore with line...
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2020-07-17
Luke Kenneth...
sigh easier to just do a line-for-line comparison of...
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Luke Kenneth...
port minerva cache fixes
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2020-07-17
Jacob Lifshay
add .pylintrc
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2020-07-17
Luke Kenneth...
forward-port minerva loadstore bugfix
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2020-07-17
Luke Kenneth...
comments
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2020-07-17
Luke Kenneth...
submodule update (again. sigh)
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2020-07-17
Luke Kenneth...
whitespace
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2020-07-17
Luke Kenneth...
use convenience vars in spr proof
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2020-07-17
Samuel A. Falvo II
Flesh out SPR-related FV properties.
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2020-07-17
Luke Kenneth...
whitespace
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2020-07-17
Luke Kenneth...
whitespace
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2020-07-17
Jacob Lifshay
add simulation-only division core using nmigen div...
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2020-07-17
Jacob Lifshay
rename DIV->Div to be consistent
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2020-07-17
Jacob Lifshay
format div code
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2020-07-17
Jacob Lifshay
add missing fixedldstcache.py to .gitignore
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2020-07-17
Jacob Lifshay
update submodule
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2020-07-16
Luke Kenneth...
whoops tried doing mtspr priv, it failed but failed...
div_pipeline
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2020-07-16
Luke Kenneth...
get shiftrot compunit working
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2020-07-16
Luke Kenneth...
more tidyup on use of CompOpSubsetBase
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2020-07-16
Luke Kenneth...
use CompOpSubsetBase in ldst record
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2020-07-16
Luke Kenneth...
sigh, bug in sprset.patch
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2020-07-16
Luke Kenneth...
update cr input record to use new CompOpSubsetBase
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2020-07-16
Luke Kenneth...
add regression test on setb simulator error
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2020-07-16
Luke Kenneth...
use CompOpSubsetBase class in Branch op record
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2020-07-16
Luke Kenneth...
get branch compunit working (missing bigendian arg)
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2020-07-16
Luke Kenneth...
get trap compunit test working, adding bigendian and msr
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2020-07-16
Luke Kenneth...
add mfmsr trap tests
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2020-07-15
Luke Kenneth...
use new CompOpSubsetBase in trap
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2020-07-15
Luke Kenneth...
remove unneeded comment in trap msin stage
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2020-07-15
Luke Kenneth...
remove unneeded comment in trap pipe_data
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2020-07-15
Luke Kenneth...
document branch pipeline relationship with PowerDecode2
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2020-07-15
Luke Kenneth...
simplify instr_is_priv
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2020-07-15
Luke Kenneth...
move traptype to soc.consts
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2020-07-15
Luke Kenneth...
add better comments on mul overflow
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2020-07-15
Luke Kenneth...
test privileged rfid call
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2020-07-15
Luke Kenneth...
spelling error
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2020-07-15
Luke Kenneth...
range of testing overflow was incorrect in mul
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2020-07-15
Luke Kenneth...
set MSR up properly for privileged mtmsr test
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2020-07-15
Luke Kenneth...
whoops forgot to update PC after trap in ISACaller
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2020-07-15
Luke Kenneth...
move priv test to above illegal/trap test
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2020-07-15
Luke Kenneth...
comments on IntegerData class
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2020-07-15
Luke Kenneth...
import PipeContext not FPPipeContext
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2020-07-15
Luke Kenneth...
minor reorg on PowerDecoder2, use switch/case rather...
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2020-07-15
Luke Kenneth...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth...
use case statement in PowerDecode2
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2020-07-15
Luke Kenneth...
select RA based on LDSTMode.update in PowerDecode2
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2020-07-15
Luke Kenneth...
add cache cx to LDSTMode
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2020-07-15
Luke Kenneth...
remove unused class XerBits
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2020-07-15
Luke Kenneth...
use Record Assert and also check muxid
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2020-07-15
Luke Kenneth...
no need to check individual port members, just check...
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2020-07-14
Luke Kenneth...
cookie-cut setup from alu proof_main_stage.py
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2020-07-14
Luke Kenneth...
reduce code size by using CompOpSubsetBase for ALU...
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2020-07-14
Luke Kenneth...
split out CompOpSubsetBase (meaning to do for a while)
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2020-07-14
Luke Kenneth...
update docstrings
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2020-07-14
Luke Kenneth...
adding MSR.PR unit test intended to activate privileged...
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2020-07-14
Luke Kenneth...
attempting to access self.msr directly
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2020-07-14
Samuel A. Falvo II
SPR: FV that should fail currently passes
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2020-07-14
Luke Kenneth...
set up masks for OP_RL* formal proof
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2020-07-14
Luke Kenneth...
add priv instruction checking to ISACaller simulator
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2020-07-14
Luke Kenneth...
add in privileged instruction decision-making in PowerD...
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2020-07-14
Luke Kenneth...
add MSR reading to issue FSM
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2020-07-14
Luke Kenneth...
comments on PowerDecode2
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2020-07-14
Luke Kenneth...
add MSR to PowerDecoder2
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