soc.git
2020-07-19 Luke Kenneth... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth... use same write_vcd for cxxsim as pysim
2020-07-19 Luke Kenneth... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-19 Luke Kenneth... add some CompUnit demo tests of the alu_fsm example
2020-07-19 Luke Kenneth... move sdir to CompFSMOpSubset in alu_fsm example
2020-07-19 Luke Kenneth... add CompFSMOpSubset, also change dir to sdir
2020-07-19 Luke Kenneth... remove unneeded import
2020-07-19 Luke Kenneth... if nmigen.sim.pysim import fails use nmigen.back.pysim
2020-07-19 Luke Kenneth... use iocontrol PrevControl / NextControl instead of...
2020-07-19 Luke Kenneth... add DivTestCase to test_issuer.py (commented out for...
2020-07-19 Cesar StraussImplement control path and unit test.
2020-07-18 Luke Kenneth... worked out that DivPipeSpec can be given a default...
2020-07-18 Luke Kenneth... missing conversion of DIV to Div
2020-07-18 Luke Kenneth... add option to generate verilog
2020-07-18 Luke Kenneth... whoops use slice not range
2020-07-18 Luke Kenneth... syntax error
2020-07-18 Cesar StraussImplement the Shifter data path
2020-07-18 Cesar StraussDocument move of the next port data
2020-07-18 Luke Kenneth... add SR latch cxxrtl backend demo
2020-07-18 Luke Kenneth... add comment and copy of pseudo-code for OP_RFID into...
2020-07-18 Luke Kenneth... review of OP_RFID showed up some errors
2020-07-18 Luke Kenneth... corrections to trap main_stage.py OP_RFID according...
2020-07-18 Samuel A. Falvo IIWIP: FV failing for unknown reasons.
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests
2020-07-18 Samuel A. Falvo IIFailing test: fast1/fast2 vs srr0/srr1? on trap pipe
2020-07-18 Samuel A. Falvo IIforgot to clean up workspace in source
2020-07-18 Samuel A. Falvo IIFV props for SC instruction
2020-07-17 Samuel A. Falvo IIFirst FV property for trap unit
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Jacob Lifshaystart adding FSMDivCore*
2020-07-17 Luke Kenneth... comment explaining why not to call self.trap in PowerDe...
2020-07-17 Luke Kenneth... likewise cut across latest Minerva loadstore with line...
2020-07-17 Luke Kenneth... sigh easier to just do a line-for-line comparison of...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth... port minerva cache fixes
2020-07-17 Jacob Lifshayadd .pylintrc
2020-07-17 Luke Kenneth... forward-port minerva loadstore bugfix
2020-07-17 Luke Kenneth... comments
2020-07-17 Luke Kenneth... submodule update (again. sigh)
2020-07-17 Luke Kenneth... whitespace
2020-07-17 Luke Kenneth... use convenience vars in spr proof
2020-07-17 Samuel A. Falvo IIFlesh out SPR-related FV properties.
2020-07-17 Luke Kenneth... whitespace
2020-07-17 Luke Kenneth... whitespace
2020-07-17 Jacob Lifshayadd simulation-only division core using nmigen div...
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-17 Jacob Lifshayadd missing fixedldstcache.py to .gitignore
2020-07-17 Jacob Lifshayupdate submodule
2020-07-16 Luke Kenneth... whoops tried doing mtspr priv, it failed but failed... div_pipeline
2020-07-16 Luke Kenneth... get shiftrot compunit working
2020-07-16 Luke Kenneth... more tidyup on use of CompOpSubsetBase
2020-07-16 Luke Kenneth... use CompOpSubsetBase in ldst record
2020-07-16 Luke Kenneth... sigh, bug in sprset.patch
2020-07-16 Luke Kenneth... update cr input record to use new CompOpSubsetBase
2020-07-16 Luke Kenneth... add regression test on setb simulator error
2020-07-16 Luke Kenneth... use CompOpSubsetBase class in Branch op record
2020-07-16 Luke Kenneth... get branch compunit working (missing bigendian arg)
2020-07-16 Luke Kenneth... get trap compunit test working, adding bigendian and msr
2020-07-16 Luke Kenneth... add mfmsr trap tests
2020-07-15 Luke Kenneth... use new CompOpSubsetBase in trap
2020-07-15 Luke Kenneth... remove unneeded comment in trap msin stage
2020-07-15 Luke Kenneth... remove unneeded comment in trap pipe_data
2020-07-15 Luke Kenneth... document branch pipeline relationship with PowerDecode2
2020-07-15 Luke Kenneth... simplify instr_is_priv
2020-07-15 Luke Kenneth... move traptype to soc.consts
2020-07-15 Luke Kenneth... add better comments on mul overflow
2020-07-15 Luke Kenneth... test privileged rfid call
2020-07-15 Luke Kenneth... spelling error
2020-07-15 Luke Kenneth... range of testing overflow was incorrect in mul
2020-07-15 Luke Kenneth... set MSR up properly for privileged mtmsr test
2020-07-15 Luke Kenneth... whoops forgot to update PC after trap in ISACaller
2020-07-15 Luke Kenneth... move priv test to above illegal/trap test
2020-07-15 Luke Kenneth... comments on IntegerData class
2020-07-15 Luke Kenneth... import PipeContext not FPPipeContext
2020-07-15 Luke Kenneth... minor reorg on PowerDecoder2, use switch/case rather...
2020-07-15 Luke Kenneth... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth... use case statement in PowerDecode2
2020-07-15 Luke Kenneth... select RA based on LDSTMode.update in PowerDecode2
2020-07-15 Luke Kenneth... add cache cx to LDSTMode
2020-07-15 Luke Kenneth... remove unused class XerBits
2020-07-15 Luke Kenneth... use Record Assert and also check muxid
2020-07-15 Luke Kenneth... no need to check individual port members, just check...
2020-07-14 Luke Kenneth... cookie-cut setup from alu proof_main_stage.py
2020-07-14 Luke Kenneth... reduce code size by using CompOpSubsetBase for ALU...
2020-07-14 Luke Kenneth... split out CompOpSubsetBase (meaning to do for a while)
2020-07-14 Luke Kenneth... update docstrings
2020-07-14 Luke Kenneth... adding MSR.PR unit test intended to activate privileged...
2020-07-14 Luke Kenneth... attempting to access self.msr directly
2020-07-14 Samuel A. Falvo IISPR: FV that should fail currently passes
2020-07-14 Luke Kenneth... set up masks for OP_RL* formal proof
2020-07-14 Luke Kenneth... add priv instruction checking to ISACaller simulator
2020-07-14 Luke Kenneth... add in privileged instruction decision-making in PowerD...
2020-07-14 Luke Kenneth... add MSR reading to issue FSM
2020-07-14 Luke Kenneth... comments on PowerDecode2
2020-07-14 Luke Kenneth... add MSR to PowerDecoder2
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