soc.git
2020-08-14 Luke Kenneth... move regspec / rdflag decoding functions out of PowerDe...
2020-08-14 Luke Kenneth... sort out instruction stop/cancel when adding a new...
2020-08-14 Luke Kenneth... put multi-ports back (for read) on int and fast regfiles
2020-08-14 Luke Kenneth... reduce decoder pathways when exception occurs
2020-08-14 Luke Kenneth... divide shiftrot pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide alu pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide logical pipe into 2 (simple phase last)
2020-08-14 Jacob Lifshayrunning the simulator works!
2020-08-13 Jacob Lifshayadd --cpu=libresoc to Makefile
2020-08-13 Luke Kenneth... fix dmi reg read
2020-08-13 Luke Kenneth... code-shuffle
2020-08-13 Luke Kenneth... remove use of latchregigister, replace with sync on...
2020-08-13 Luke Kenneth... sync on pc writing when changed
2020-08-13 Cole Poirierdcache.py add initial imports
2020-08-13 Cole Poiriermem_types.py add more types from common.vhdl
2020-08-13 Cole Poiriermove memory related types from mmu.py into new file...
2020-08-13 Luke Kenneth... sync on reset in compalu
2020-08-13 Luke Kenneth... add forwarding-bus mode to Regfile Memory (and disable it)
2020-08-13 Luke Kenneth... sync on port interface address in ld/st compunit, and...
2020-08-13 Luke Kenneth... another sync to cut latency
2020-08-13 Cole PoirierInitial commit of translation of microwatt dcache.vhdl...
2020-08-13 Luke Kenneth... remove latchregister, sync src oper_i into MultiCompUnit
2020-08-13 Luke Kenneth... minor tidyup on alu compunit:
2020-08-13 Luke Kenneth... plenty of time to wait for operand, so use "sync" in...
2020-08-13 Luke Kenneth... sigh. convert Fast regfile to binary
2020-08-13 Luke Kenneth... sync on read of regfile ports
2020-08-13 Luke Kenneth... sigh. convert INT regfile to binary addressing
2020-08-13 Luke Kenneth... create a RegFileMem class that uses Memory
2020-08-12 Jacob Lifshayadd run_sim to Makefile
2020-08-12 Cole Poiriermmu.py add skeleton sim and test functions from regfile...
2020-08-12 Cole PoirierDelete unnecessary mmu dir, move mmu.py out of mmu...
2020-08-12 Cole PoirierRevert "Remove mmu dir and associated mmu/test/ dir...
2020-08-12 Cole PoirierRemove mmu dir and associated mmu/test/ dir
2020-08-12 Cole PoirierRemove rst signals, fix len of hex Consts, fix variable...
2020-08-12 Cole PoirierCreate dir experiment/mmu then mmu/test with skeleton...
2020-08-12 Cole Poiriermmu.py add RecordObject classes from common.vhdl input...
2020-08-12 Cole Poiriermmu.py remove TODOs for vhdl (others => '0') as they...
2020-08-12 Cole Poiriermmu.py fix or(block of logic) to be (block of logic...
2020-08-12 Cole Poiriermmu.py fix length of hex const https://bugs.libre-soc...
2020-08-12 Cole Poiriermmu.py remove class AddrShifter
2020-08-12 Cole PoirierFix typo in mmu.py
2020-08-11 Cole Poiriermmu.py fix formatting, use Cat() where '&' in mmu.vhdl
2020-08-11 Tobias Plateninitial version of L0CacheBuffer2
2020-08-11 Luke Kenneth... sigh, remove yet another int regfile read port
2020-08-11 Luke Kenneth... massive reduction in gate count by using alternative...
2020-08-11 Luke Kenneth... reduce regfile port usage for INT and FAST
2020-08-11 Luke Kenneth... prepare write ports to be shared
2020-08-11 Luke Kenneth... move write regfile picker creation to new function
2020-08-11 Luke Kenneth... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth... whoops fix change of variable (state) msr/pc
2020-08-11 Luke Kenneth... reducing regfile port usage by sharing read ports
2020-08-10 Samuel A. Falvo IIWIP!! Make MUL pipeline proof run again.
2020-08-10 Cole PoirierFix typo in mmu.py
2020-08-10 Cole PoirierFix typo mmu.py
2020-08-10 Cole PoirierGlobal search and replace (^, |), fixes bug 450 comment...
2020-08-10 Cole Poirierfix bug 450 comments 8,9,10
2020-08-10 Cole PoirierFix bug 450 comment 7
2020-08-10 Cole Poiriermmu.py add line I forgot to translate from mmu.vhdl
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-10 Cole Poiriermmu.vhdl translation to mmu.py 95 percent complete
2020-08-09 Luke Kenneth... stop combinatorial loop in pi2ls
2020-08-09 Luke Kenneth... write pulse in issuer
2020-08-09 Luke Kenneth... fix combinatorial loop in ldst compunit
2020-08-09 Luke Kenneth... use rising edge detection on st go_i/rel_o
2020-08-09 Luke Kenneth... add logical test issuer case
2020-08-09 Luke Kenneth... get rid of MSR read combinatorial loop
2020-08-09 Luke Kenneth... delay go_st by one cycle, break combinatorial loop
2020-08-09 Luke Kenneth... divwo case makes test_issuer stay busy!
2020-08-09 Luke Kenneth... add extra divwo regression test
2020-08-09 Luke Kenneth... compalu combinatorial loop detected
2020-08-08 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-08 Cole PoirierUpdate test case_mulli
2020-08-08 Tobias Platenaddr_split.py: shift bytes not bits
2020-08-07 Cole PoirierUpdate test case_mulli
2020-08-07 Cole PoirierUpdate test case_mulli, I think it now works correctly
2020-08-07 Cole PoirierUpdate mulli to try to use immediates not registers
2020-08-06 Cole PoirierFix mmu.py formatting
2020-08-06 Cole PoirierFix formatting
2020-08-06 Cole PoirierInitial commit of translation of microwatt mmu.vhdl...
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Luke Kenneth... fix LDST PortInterface FSM interaction
2020-08-06 Luke Kenneth... MULS on parameter b needed to check whether it was...
2020-08-06 Cole PoirierAdd special test for case_mulli, apply autopep8
2020-08-05 Cole PoirierAdd test case_all_rb_close_to_ov
2020-08-05 Cole PoirierRemove mulli from instrs in test case_all*, add TODO...
2020-08-05 Cole PoirierAdd new test_values to tests case_all and case_all_rb_r...
2020-08-05 Cole PoirierAdd second case_all test where rb is randint
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-05 Tobias Platenundo changes that fix unit test, but do not solve anything
2020-08-05 Luke Kenneth... rename ibus/dbus (shorten)
2020-08-05 Luke Kenneth... clear sel on loadstore
2020-08-05 Tobias Platenfix LDSTSplitter
2020-08-05 Cole PoirierRemove madd* isns, added madd* isns test TODO
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth... adding bus data width of 64 in litex sim doesnt work
2020-08-05 Luke Kenneth... add div test cases into test_issuer.py
2020-08-05 Luke Kenneth... add div FSM as default for test_issuer in verilog and...
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
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