soc.git
2020-08-21 Luke Kenneth... ld/st bus reduction test operational
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-21 Luke Kenneth... comment formatting
2020-08-21 Luke Kenneth... remove default values
2020-08-21 Luke Kenneth... just range(the_constant)
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered.
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry...
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP.
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u)
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface
2020-08-20 Tobias Platentestcase refactoring
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface
2020-08-20 Luke Kenneth... bugfix wishbone downconvert using wb sram 64-to-32...
2020-08-20 Luke Kenneth... add a wishbone upconverter
2020-08-19 Luke Kenneth... rename and document fields in shift_rot proof
2020-08-19 Luke Kenneth... comments in dcache
2020-08-19 Luke Kenneth... more subtle interactions between wishbone bus when...
2020-08-19 Luke Kenneth... bit of a reorg of mul proof, tracking down missing
2020-08-19 Luke Kenneth... move long mul tests to separate unit test
2020-08-19 Luke Kenneth... use "Mask" class which is more gate-efficient than...
2020-08-19 Samuel A. Falvo IIWIP: OP_MUL proofs started.
2020-08-19 Luke Kenneth... set up StageChain of 3 mul stages
2020-08-18 Cole Poirierfu/mul/test/test_pipe_caller.py test case_all_rb_close_...
2020-08-18 Tobias Platenadd testcase for LDSTSplitter using PortInterface
2020-08-18 Luke Kenneth... fix spr state test
2020-08-18 Luke Kenneth... add comment in dcache.py
2020-08-17 Cole Poirierdcache.py commit today's progress on translating dcache...
2020-08-17 Cole PoirierCreate file experiment/wb_types.py to mirror microwatt...
2020-08-17 Luke Kenneth... move Mask to nmutil
2020-08-17 Luke Kenneth... turn SelectableInt less/greater into signed versions.
2020-08-17 Luke Kenneth... use longer memtest in litex sim
2020-08-17 Luke Kenneth... adjust litex bios cmp test
2020-08-17 Luke Kenneth... fix signed variants of cmp in alu
2020-08-17 Luke Kenneth... add new cmp test for alu
2020-08-17 Luke Kenneth... use shift module in mmu. to be moved to nmutil
2020-08-16 Cole Poiriermmu.py fix formatting 80 char limit
2020-08-16 Luke Kenneth... attempting to track down bug in litex bios memtest
2020-08-16 Luke Kenneth... read delay on getting regfile data
2020-08-16 Luke Kenneth... limit debug reporting in litex sim to range of pc
2020-08-16 Luke Kenneth... cmp test from litex bios
2020-08-16 Luke Kenneth... remove vhdl comments
2020-08-16 Luke Kenneth... use simple one-line mask-generation
2020-08-16 Luke Kenneth... fix LD/ST pimem issue with rising_edge detection
2020-08-16 Luke Kenneth... missing vars, spelling corrections
2020-08-16 Luke Kenneth... big reorg, shuffle code to functions, makes the FSM...
2020-08-16 Luke Kenneth... spelling error, move perm_ok to local
2020-08-16 Luke Kenneth... more comment removal
2020-08-16 Luke Kenneth... more remove comments
2020-08-16 Luke Kenneth... removing more comments, tidyup
2020-08-16 Luke Kenneth... restore incorrect removal of zero-Cat at LHS (should...
2020-08-16 Luke Kenneth... continue tidyup, comment removal/review. use byte_reve...
2020-08-16 Luke Kenneth... fix batch of syntax errors found by running mmu.py
2020-08-16 Luke Kenneth... begin tidyup, removing comments after line-by-line...
2020-08-15 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-15 Cole Poiriermmu.py fix Cat() semantics fixes https://bugs.libre...
2020-08-15 Luke Kenneth... thanks to daveshah, added simulation of dram
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Luke Kenneth... rather big change to interaction between regfile and...
2020-08-15 Luke Kenneth... clear compalu data latch always on issue
2020-08-15 Cesar StraussDemonstrates string traces
2020-08-15 Cesar StraussDemonstrates adding extra debug signals traces to the...
2020-08-15 Cesar StraussDemonstrates creating stylish GTKWave "save" files...
2020-08-14 Luke Kenneth... remove latchregister, use sync to capture compunit...
2020-08-14 Luke Kenneth... ha! "state" (pc, msr) not properly passed to core
2020-08-14 Luke Kenneth... drop in insn_state synchronously in issuer, at same...
2020-08-14 Luke Kenneth... submodule update
2020-08-14 Luke Kenneth... hrfid unit test sets up HSRR0 and HSRR1
2020-08-14 Luke Kenneth... bad hack to get HSRR0/1 to be "same" as SRR0/1
2020-08-14 Luke Kenneth... bug in isa parser not recognising MSR as declared variable
2020-08-14 Luke Kenneth... hack to get hrfid not to alter msr 51
2020-08-14 Luke Kenneth... stop trying to read swap files
2020-08-14 Luke Kenneth... sync on alu results in compalu
2020-08-14 Luke Kenneth... update submodule, add hrfid
2020-08-14 Luke Kenneth... update submodule, add hrfid
2020-08-14 Luke Kenneth... finally, fix decoder combinatorial loop
2020-08-14 Luke Kenneth... fix test_compunit.py after moving decoder rdflags function
2020-08-14 Luke Kenneth... add hrfid unit test
2020-08-14 Luke Kenneth... sync up the core decode-execute state,
2020-08-14 Luke Kenneth... move instruction decoder out of core
2020-08-14 Luke Kenneth... move regspec / rdflag decoding functions out of PowerDe...
2020-08-14 Luke Kenneth... sort out instruction stop/cancel when adding a new...
2020-08-14 Luke Kenneth... put multi-ports back (for read) on int and fast regfiles
2020-08-14 Luke Kenneth... reduce decoder pathways when exception occurs
2020-08-14 Luke Kenneth... divide shiftrot pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide alu pipeline into 2 (simple last)
2020-08-14 Luke Kenneth... divide logical pipe into 2 (simple phase last)
2020-08-14 Jacob Lifshayrunning the simulator works!
2020-08-13 Jacob Lifshayadd --cpu=libresoc to Makefile
2020-08-13 Luke Kenneth... fix dmi reg read
2020-08-13 Luke Kenneth... code-shuffle
2020-08-13 Luke Kenneth... remove use of latchregigister, replace with sync on...
2020-08-13 Luke Kenneth... sync on pc writing when changed
2020-08-13 Cole Poirierdcache.py add initial imports
next