2021-02-21 |
Luke Kenneth... | add JTAG enable/disable of 4k SRAMs |
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2021-02-21 |
Cesar Strauss | The new version of "sel" is smart enough to find a... |
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2021-02-21 |
Luke Kenneth... | add comments for Mode field in SVP64Asm |
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2021-02-21 |
Luke Kenneth... | comments in SVP64RMFields |
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2021-02-21 |
Cesar Strauss | Use the new selection field function from nmutil |
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2021-02-21 |
Cesar Strauss | Use symbolic values as field sizes |
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2021-02-21 |
Cesar Strauss | Replace all hardcoded shifts into RM by usage of SVP64R... |
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2021-02-21 |
Luke Kenneth... | create SVP64CROffs consts for when SVP64 Vector-of... |
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2021-02-20 |
Luke Kenneth... | comments on sv.add. Rc=1 unit test |
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2021-02-20 |
Luke Kenneth... | add in Vectorised CRs when Rc=1 into ISACaller |
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2021-02-20 |
Luke Kenneth... | add CR1 to DecodeCRIn/Out |
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2021-02-20 |
Luke Kenneth... | add some debug checking to get_pdecode_cr_out |
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2021-02-20 |
Luke Kenneth... | add crossreference to bug #603 |
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2021-02-20 |
Luke Kenneth... | add more debug output to get_pdecode_cr_out |
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2021-02-20 |
Cesar Strauss | Actually forward the field width to field_slice() |
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2021-02-20 |
Cesar Strauss | Assemble the SV64 prefix from its subfields using SVP64... |
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2021-02-20 |
Luke Kenneth... | start on CRs in SVP64 mode |
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2021-02-20 |
Luke Kenneth... | fix SVP64Asm Rc=1 assembly |
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2021-02-20 |
Luke Kenneth... | add black-box attribute to 4k SRAM cell |
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2021-02-20 |
Cesar Strauss | Fix more MSB0 issues in comments |
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2021-02-20 |
Cesar Strauss | Replace more hardcoded constants with symbolic field... |
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2021-02-20 |
Luke Kenneth... | increment CRs based on srcstep, see what happens |
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2021-02-20 |
Luke Kenneth... | add litex wishbone interconnect to 4x 4k SRAMs |
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2021-02-20 |
Luke Kenneth... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... |
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2021-02-20 |
Luke Kenneth... | add option for QTY 4x 4k SRAM blocks (not added yet... |
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2021-02-20 |
Luke Kenneth... | add Wishbone-wrapped SPBlock_512W64B8W |
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2021-02-20 |
Luke Kenneth... | whoops set ROM to none by mistake |
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2021-02-20 |
Luke Kenneth... | whoops spelling error |
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2021-02-20 |
Luke Kenneth... | add (unused) code for writing out SVSTATE in TestIssuer |
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2021-02-20 |
Luke Kenneth... | correct arguments, set microwatt_mmu=True, pass in... |
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2021-02-20 |
Luke Kenneth... | minor whitespace cleanup |
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2021-02-20 |
Luke Kenneth... | remove massive code-duplication, move simple "self... |
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2021-02-20 |
Tobias Platen | mmu testcase: set MMU SPRs |
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2021-02-20 |
Tobias Platen | add rom debugger |
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2021-02-20 |
Tobias Platen | add mmu rom testcase |
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2021-02-18 |
Tobias Platen | mmu: remove TestMemory |
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2021-02-17 |
Luke Kenneth... | declare blank classes SPEC and EXTRA2 to add MSB-to... |
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2021-02-17 |
Cesar Strauss | Use subfield bit selection to extract the RM SVP64... |
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2021-02-17 |
Cesar Strauss | Replace MSB-i by symbolic subfield indices and selectors |
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2021-02-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-17 |
Tobias Platen | add wishbone signals to gtkwave output |
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2021-02-17 |
Cesar Strauss | Add the SVSTATE traces to GTKWave to allow debugging... |
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2021-02-17 |
Cesar Strauss | Initialize the core SVSTATE from the corresponding... |
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2021-02-17 |
Cesar Strauss | Revert "Setup SVSTATE, from the test settings, at the... |
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2021-02-17 |
Cesar Strauss | Add a function to select bits from a signal into a... |
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2021-02-17 |
Luke Kenneth... | fix reg read/write in ISACaller, PowerDecoder2 handles... |
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2021-02-17 |
Cesar Strauss | Add a case for checking the EXTRA field and register... |
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2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
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2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
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2021-02-16 |
Cesar Strauss | Fix MSB0 issues for SVP64 |
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2021-02-16 |
Tobias Platen | mmureq handling |
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2021-02-16 |
Tobias Platen | dcache error handling |
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2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-16 |
Luke Kenneth... | ordering wrong on svstate in ISACaller |
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2021-02-16 |
Luke Kenneth... | adapt botchify so it can be used for 31- or 15- etc... |
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2021-02-16 |
Luke Kenneth... | add indicator to PowerDecoder2 when no outputs are... |
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2021-02-15 |
Cole Poirier | remove file experiment/formal/proof_icache.py as it... |
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2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
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2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
commit | commitdiff | tree |
2021-02-14 |
Cesar Strauss | Show traces for the register numbers of the current... |
commit | commitdiff | tree |
2021-02-14 |
Cesar Strauss | Fix width of the "extra" input on the Extra decoder |
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2021-02-14 |
Cesar Strauss | Fix conversion to MSB0 |
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2021-02-14 |
Cesar Strauss | Remove obsolete comment |
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2021-02-14 |
Luke Kenneth... | add comments to TestIssuer |
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2021-02-14 |
Luke Kenneth... | add srcstep onto Vectorised GPRs in PowerDecoder2 |
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2021-02-14 |
Luke Kenneth... | add TestRunner comments |
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2021-02-14 |
Luke Kenneth... | add Regfiles comments |
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2021-02-14 |
Luke Kenneth... | add SVSTATE reading to TestIssuer |
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2021-02-14 |
Luke Kenneth... | add SVSTATE to CoreState |
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2021-02-14 |
Luke Kenneth... | add extra FSM explanatory comments to TestIssuer |
commit | commitdiff | tree |
2021-02-13 |
Luke Kenneth... | use function for getting instruction from 32/64 bit... |
commit | commitdiff | tree |
2021-02-13 |
Cesar Strauss | Fetch and decode the SVP64 prefix |
commit | commitdiff | tree |
2021-02-13 |
Tobias Platen | OP_TLBIE must in be instr_is_priv |
commit | commitdiff | tree |
2021-02-13 |
Tobias Platen | keep commits to under 80 chars |
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2021-02-13 |
Cesar Strauss | Check the PC value at the end of each instruction |
commit | commitdiff | tree |
2021-02-13 |
Cesar Strauss | Skip vector test case, and add a scalar case |
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2021-02-13 |
Cesar Strauss | Fix imports and whitespace |
commit | commitdiff | tree |
2021-02-13 |
Luke Kenneth... | update svp64 unit test comments |
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2021-02-13 |
Tobias Platen | forward microwatt mmu specific SPR: PID and PRTBL |
commit | commitdiff | tree |
2021-02-13 |
Luke Kenneth... | add SVP64 TestIssuer separate unit test |
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2021-02-13 |
Luke Kenneth... | split out TestRunner into separate module |
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2021-02-13 |
Cesar Strauss | Fix SVP64 translator to yield the unaltered instruction |
commit | commitdiff | tree |
2021-02-12 |
Luke Kenneth... | add one SVP64 ALU test case to get started |
commit | commitdiff | tree |
2021-02-12 |
Luke Kenneth... | add SVSTATE to TestCase infrastructure for use in TestI... |
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2021-02-12 |
Luke Kenneth... | add skip of instruction if SVSTATE.VL=0 in ISACaller |
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2021-02-12 |
Luke Kenneth... | validate all registers to make sure no damage occurs... |
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2021-02-12 |
Luke Kenneth... | add srcstep and correct PC-advancing during Sub-PC... |
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2021-02-12 |
Luke Kenneth... | comments |
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2021-02-12 |
Luke Kenneth... | add in SVSTATE.srcstep update, loop from 0 to VL-1 |
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2021-02-12 |
Luke Kenneth... | allow PC to update by 8 in SVP64 mode |
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2021-02-12 |
Luke Kenneth... | fix setting of SVSTATE.VL and MVL |
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2021-02-12 |
Luke Kenneth... | add in SVSTATE to ISACaller, not used, just passed in |
commit | commitdiff | tree |
2021-02-11 |
Luke Kenneth... | comments in TestIssuer for SVP64PrefixDecoder |
commit | commitdiff | tree |
2021-02-10 |
Luke Kenneth... | add svp64 reg decode detection to ISACaller output |
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2021-02-10 |
Luke Kenneth... | starting to add SVP64 register EXTRA-read and isvec... |
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2021-02-10 |
Luke Kenneth... | comment update |
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2021-02-09 |
colepoirier | add missing newline at end of experiment/formal/.gitignore |
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2021-02-09 |
colepoirier | fix erroneous removal of proof* from experiment/formal... |
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2021-02-07 |
colepoirier | add skeleton implementation of experiment/formal/proof_... |
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