soc.git
2020-08-23 Cesar StraussAdd comment node type
2020-08-23 Cesar StraussAdd base and display styles
2020-08-23 Cesar StraussApply style from node own name
2020-08-23 Cesar StraussAdd color style
2020-08-23 Cesar StraussCollect styles from the tuple
2020-08-23 Cesar StraussPropagate the root style to all signals
2020-08-23 Luke Kenneth... comment why litex sim mem map is altered
2020-08-23 Luke Kenneth... multiply does not have invert_in, zero_a or invert_out
2020-08-22 Luke Kenneth... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth... update submodule
2020-08-22 Luke Kenneth... load bios not 1.bin unit test
2020-08-22 Luke Kenneth... add extra div regression tests
2020-08-22 Cesar StraussMove comments to the docstring
2020-08-22 Cesar StraussWalk the DOM and emit the trace names
2020-08-22 Luke Kenneth... add eqv to logical unit test
2020-08-22 Luke Kenneth... add nor and nand to unit test
2020-08-22 Luke Kenneth... moved to div pipe temporarily in compunits
2020-08-22 Luke Kenneth... bug in andc and orc, complement was taking place on...
2020-08-22 Luke Kenneth... extend addis test
2020-08-22 Luke Kenneth... add andc and orc tests, failing because RB needs invers...
2020-08-22 Luke Kenneth... modsd bug, https://bugs.libre-soc.org/show_bug.cgi...
2020-08-22 Cesar StraussFirst draft of a mini-language to describe GTKWave...
2020-08-22 Luke Kenneth... submodule update
2020-08-22 Luke Kenneth... add regression test for nonzero addis
2020-08-22 Luke Kenneth... add means to run microwatt test binaries
2020-08-22 Luke Kenneth... r0 zero tests on addis, fails
2020-08-22 Luke Kenneth... investigating litex sdrinit function
2020-08-22 Luke Kenneth... add pseudo-op conversion
2020-08-22 Luke Kenneth... add start of litex bios counter loop
2020-08-21 Luke Kenneth... remove extraneous comments
2020-08-21 Luke Kenneth... testing 64-bit wishbone bus after 32-bit *still* fails...
2020-08-21 Tobias Platentypo fix in test_l0_cache_buffer2.py
2020-08-21 Cole Poirierdcache.py fix asserts, use backslash and two strings...
2020-08-21 Cole Poirierdcache.py replace functions that return signals with...
2020-08-21 Cole Poirierwb_types fix typo
2020-08-21 Tobias Platenconnect TestCachedMemoryPortInterface to LDSTSplitter
2020-08-21 Luke Kenneth... get litex sim enabled with 32-bit wishbone bus
2020-08-21 Luke Kenneth... ld/st bus reduction test operational
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-21 Luke Kenneth... comment formatting
2020-08-21 Luke Kenneth... remove default values
2020-08-21 Luke Kenneth... just range(the_constant)
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered.
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry...
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP.
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u)
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface
2020-08-20 Tobias Platentestcase refactoring
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface
2020-08-20 Luke Kenneth... bugfix wishbone downconvert using wb sram 64-to-32...
2020-08-20 Luke Kenneth... add a wishbone upconverter
2020-08-19 Luke Kenneth... rename and document fields in shift_rot proof
2020-08-19 Luke Kenneth... comments in dcache
2020-08-19 Luke Kenneth... more subtle interactions between wishbone bus when...
2020-08-19 Luke Kenneth... bit of a reorg of mul proof, tracking down missing
2020-08-19 Luke Kenneth... move long mul tests to separate unit test
2020-08-19 Luke Kenneth... use "Mask" class which is more gate-efficient than...
2020-08-19 Samuel A. Falvo IIWIP: OP_MUL proofs started.
2020-08-19 Luke Kenneth... set up StageChain of 3 mul stages
2020-08-18 Cole Poirierfu/mul/test/test_pipe_caller.py test case_all_rb_close_...
2020-08-18 Tobias Platenadd testcase for LDSTSplitter using PortInterface
2020-08-18 Luke Kenneth... fix spr state test
2020-08-18 Luke Kenneth... add comment in dcache.py
2020-08-17 Cole Poirierdcache.py commit today's progress on translating dcache...
2020-08-17 Cole PoirierCreate file experiment/wb_types.py to mirror microwatt...
2020-08-17 Luke Kenneth... move Mask to nmutil
2020-08-17 Luke Kenneth... turn SelectableInt less/greater into signed versions.
2020-08-17 Luke Kenneth... use longer memtest in litex sim
2020-08-17 Luke Kenneth... adjust litex bios cmp test
2020-08-17 Luke Kenneth... fix signed variants of cmp in alu
2020-08-17 Luke Kenneth... add new cmp test for alu
2020-08-17 Luke Kenneth... use shift module in mmu. to be moved to nmutil
2020-08-16 Cole Poiriermmu.py fix formatting 80 char limit
2020-08-16 Luke Kenneth... attempting to track down bug in litex bios memtest
2020-08-16 Luke Kenneth... read delay on getting regfile data
2020-08-16 Luke Kenneth... limit debug reporting in litex sim to range of pc
2020-08-16 Luke Kenneth... cmp test from litex bios
2020-08-16 Luke Kenneth... remove vhdl comments
2020-08-16 Luke Kenneth... use simple one-line mask-generation
2020-08-16 Luke Kenneth... fix LD/ST pimem issue with rising_edge detection
2020-08-16 Luke Kenneth... missing vars, spelling corrections
2020-08-16 Luke Kenneth... big reorg, shuffle code to functions, makes the FSM...
2020-08-16 Luke Kenneth... spelling error, move perm_ok to local
2020-08-16 Luke Kenneth... more comment removal
2020-08-16 Luke Kenneth... more remove comments
2020-08-16 Luke Kenneth... removing more comments, tidyup
2020-08-16 Luke Kenneth... restore incorrect removal of zero-Cat at LHS (should...
2020-08-16 Luke Kenneth... continue tidyup, comment removal/review. use byte_reve...
2020-08-16 Luke Kenneth... fix batch of syntax errors found by running mmu.py
2020-08-16 Luke Kenneth... begin tidyup, removing comments after line-by-line...
2020-08-15 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-15 Cole Poiriermmu.py fix Cat() semantics fixes https://bugs.libre...
2020-08-15 Luke Kenneth... thanks to daveshah, added simulation of dram
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
2020-08-15 Cole Poiriermmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
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