soc.git
2020-06-02 Cesar StraussAllow at least one operand to be fetched
2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
2020-06-01 Luke Kenneth... remove reading port 3 for CR pipeline. RS moved to...
2020-06-01 Luke Kenneth... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth... add test_bc_reg (fails)
2020-06-01 Luke Kenneth... remove unneeded fields from Decode2Execute1Type
2020-06-01 Michael NolanAdd proof for RegFile
2020-06-01 Luke Kenneth... more unneeded fields from SR InputRecord
2020-06-01 Luke Kenneth... remove data_len from SR input record
2020-06-01 Luke Kenneth... remove zero/invert from ShiftRot Input Record
2020-06-01 Luke Kenneth... add shift-rot input record and use it
2020-06-01 Luke Kenneth... CompBROpSubset exists
2020-06-01 Luke Kenneth... RS moved to port 1 (from port 3), remove need in ALU...
2020-06-01 Michael NolanAdd proof for RegFileArray
2020-06-01 Luke Kenneth... remove use of reg3 in logical pipeline: CSV files moved...
2020-06-01 Michael NolanHave regfile use AnySeq instead of AnyConst
2020-06-01 Luke Kenneth... rotator carry is set into both XER CA and CA32 fields
2020-06-01 Luke Kenneth... comment out rlwinm. for now
2020-06-01 Luke Kenneth... argh - need to zero the src_i input after "Read" is...
2020-06-01 Michael NolanEnable k-induction for register file proof
2020-06-01 Michael NolanThat was weird. For some reason it wasn't generating...
2020-06-01 Michael NolanFull BMC proof of Register
2020-06-01 Michael NolanBegin rewrite of proof_regfile.py
2020-06-01 Luke Kenneth... put RB in 2nd position (matching immediate) in ShiftRot...
2020-06-01 Luke Kenneth... sigh - another instance where write-mask needed to...
2020-06-01 Luke Kenneth... remove xer so/ov, swap rs/rb to correct(?) order in...
2020-06-01 Tobias Platenproof_datamerger wip
2020-06-01 Luke Kenneth... add rlwinm. test instruction (sets CR0)
2020-06-01 Luke Kenneth... remove duplicate signal
2020-06-01 Luke Kenneth... allow ALU / Logical ops to select RS as 1st operand
2020-06-01 Luke Kenneth... allow M*-Form shiftrot to swap RS/RB back to consistent...
2020-06-01 Luke Kenneth... add first version of ShiftRot CompUnit test
2020-06-01 Luke Kenneth... shiftrot uses LogicalOutputData not ALUOutputData
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-06-01 Luke Kenneth... add assertions for branch compunit output
2020-06-01 Luke Kenneth... invert SPR1/2 in branch output data
2020-06-01 Luke Kenneth... decode SPRs for branch
2020-06-01 Luke Kenneth... swap over SPR1/2 to fit with microwatt SPR conventions
2020-06-01 Luke Kenneth... add first version compunit branch test
2020-06-01 Luke Kenneth... whoops need to read RS in CR inputs test
2020-06-01 Luke Kenneth... add first version of CR CompUnit test
2020-06-01 Luke Kenneth... minor adjustment, zero test in ALU output stage
2020-06-01 Luke Kenneth... remove unneeded code
2020-05-31 Luke Kenneth... bit-test on the function-unit value being tested
2020-05-31 Luke Kenneth... update isatables to cmpb not modifying CR0
2020-05-31 Luke Kenneth... add logical compunit test
2020-05-31 Luke Kenneth... comment inputs and outputs from ALU unit test
2020-05-31 Luke Kenneth... imports - use of globals. baaaad
2020-05-31 Luke Kenneth... remove unneeded code and inputs. convert to "naming...
2020-05-31 Luke Kenneth... split out common code from test_alu_compunit.py
2020-05-31 Luke Kenneth... add comments for MultiCompUnit parallel test
2020-05-31 Luke Kenneth... de-hard-code-ify getting results from MultiCompUnit
2020-05-31 Luke Kenneth... remove unneeded imports
2020-05-31 Luke Kenneth... split out compalu unit tests to separate module (gettin...
2020-05-31 Luke Kenneth... HA! found a bug in MultiCompUnit handling of write...
2020-05-31 Luke Kenneth... clarify
2020-05-31 Luke Kenneth... OP_CMPEQB also requesting change of output reg (stop...
2020-05-31 Luke Kenneth... OP_CMP is requesting a change of the output register...
2020-05-31 Luke Kenneth... still investigating
2020-05-31 Luke Kenneth... start with zero, try not to compare against 9 bytes...
2020-05-31 Luke Kenneth... more debug statements
2020-05-31 Luke Kenneth... add in more CR debug statements
2020-05-31 Luke Kenneth... copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
2020-05-31 Luke Kenneth... remove commented-out vars from ALU input record
2020-05-31 Luke Kenneth... write cr0 when op.write_cr.ok is set
2020-05-31 Luke Kenneth... add write_cr to ALU record subset
2020-05-31 Luke Kenneth... comment out xer ov/so for now
2020-05-30 Luke Kenneth... get carry from cr write_cr
2020-05-30 Luke Kenneth... select CR0 write out only when RC=1
2020-05-30 Luke Kenneth... set CR0 output when OP_CMP or OP_CMPEQB need it
2020-05-30 Luke Kenneth... add in use of "Settle"
2020-05-30 Luke Kenneth... add in write-mask into MultiCompUnit and MCU-ALU unit...
2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-30 Tobias Platenunit test for DataMerger
2020-05-30 Luke Kenneth... create read-mask for ALU CompUnit: switches off optiona...
2020-05-30 Luke Kenneth... create a write-mask, anything with an "ok" in the Recor...
2020-05-30 Luke Kenneth... allow MultiCompUnit outputs to be Records, to capture...
2020-05-30 Luke Kenneth... add read-mask to MultiCompUnit
2020-05-30 Luke Kenneth... code-shuffle / comments
2020-05-30 Luke Kenneth... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth... order of XER so/ca wrong way round from regspec
2020-05-30 Luke Kenneth... still experimenting with ALU-CompUnit interaction
2020-05-29 Luke Kenneth... interesting. use of Settle() works, showing that Regfi...
2020-05-29 Luke Kenneth... module comments for popcount
2020-05-29 Luke Kenneth... comments on popcount
2020-05-29 Luke Kenneth... trigger ALU ready when operands ready
2020-05-29 Tobias Platenfixes for DataMerger
2020-05-29 Luke Kenneth... trigger read ALU ready/valid from latch as well
2020-05-29 Luke Kenneth... use a latch to communicate read/valid output from ALU
2020-05-29 Tobias PlatenDataMerger: rename addr_match_i to addr_array_i
2020-05-29 Tobias Platenfixed 'return m is missing'
2020-05-29 Tobias Platenwhitespace fixes
2020-05-29 Luke Kenneth... latch all output on ALU output valid
2020-05-29 Luke Kenneth... create read-done pulse
2020-05-29 Luke Kenneth... write-release moves out of "ALU valid" due to using...
2020-05-29 Luke Kenneth... signal start of request from when ALU triggers result...
2020-05-29 Luke Kenneth... create rising pulse from ALU valid
2020-05-29 Luke Kenneth... names of attributes needs to be dest_o not dest_i
2020-05-29 Luke Kenneth... rename output signals in Test ALU
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