soc.git
2020-06-29 Luke Kenneth... sort out syntax errors in div
2020-06-29 Luke Kenneth... first unit test for div
2020-06-29 Luke Kenneth... update submodule to fix div bug
2020-06-29 Luke Kenneth... add ignore for parsetab.py
2020-06-29 Luke Kenneth... add autogenerated do not commit comment
2020-06-29 Luke Kenneth... update submodule to div overflow
2020-06-29 Luke Kenneth... separate out divide by zero cases
2020-06-29 Luke Kenneth... update OV and OV32 ISACaller flags if overflow occurs
2020-06-29 Luke Kenneth... attempting to add overflow setting in ISACaller
2020-06-29 Luke Kenneth... whoops, hex parser digits are in multiples of 4 bits
2020-06-29 Luke Kenneth... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Luke Kenneth... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth... need args to WishboneArbiter, match data width size
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth... add test instruction memory
2020-06-28 Luke Kenneth... add readonly option to TestMemory
2020-06-28 Luke Kenneth... expand instruction bus width to 64 bit, start on a...
2020-06-28 Luke Kenneth... parameterise minerva i-cache
2020-06-28 Luke Kenneth... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth... sram address do not cut by LSBs
2020-06-28 Luke Kenneth... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth... use PortInterface connect_port
2020-06-28 Luke Kenneth... use PortInterface connect_port
2020-06-28 Luke Kenneth... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth... name issue in Pi2LSUI
2020-06-26 Luke Kenneth... whitespace and imports
2020-06-26 Luke Kenneth... whitespace
2020-06-26 Luke Kenneth... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth... correct address in pi2ls
2020-06-26 Luke Kenneth... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth... add in LenExpand shift/mask
2020-06-26 Luke Kenneth... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth... unit test broken is ok :)
2020-06-26 Luke Kenneth... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth... whitespace
2020-06-26 Luke Kenneth... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth... halve the test memory size again
2020-06-26 Luke Kenneth... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth... add reconfigureable Load/Store class
2020-06-26 Luke Kenneth... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth... add nmigen-soc to dependencies
2020-06-25 Luke Kenneth... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth... move comments to minerva LoadStoreInterface
2020-06-24 Luke Kenneth... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth... annoying error in latest nmigen
2020-06-23 Luke Kenneth... TstL0CacheBuffer returns array of ports differently now
2020-06-22 Luke Kenneth... remove unused module
2020-06-22 Luke Kenneth... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth... comments for LDST CompUnit test
next