2020-05-25 |
Luke Kenneth... | add docstring |
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2020-05-25 |
Luke Kenneth... | add INT, SPR and CR regfiles |
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2020-05-25 |
Tobias Platen | refactoring (see #216 Comment 43) |
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2020-05-25 |
Tobias Platen | whitespace changes |
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2020-05-25 |
Luke Kenneth... | quick addition of zero+immed test to LDSTCompUnit |
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2020-05-25 |
Luke Kenneth... | must not do rd-req checking when both imm and zero... |
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2020-05-25 |
Tobias Platen | implement DataMerger interface |
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2020-05-25 |
Luke Kenneth... | add zero immed on LDST, untested |
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2020-05-25 |
Luke Kenneth... | comment out invalid test |
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2020-05-25 |
Luke Kenneth... | lots of greater than 80 chars |
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2020-05-25 |
Luke Kenneth... | switch out req rel if immediate enabled |
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2020-05-25 |
Cesar Strauss | Show oper_r and oper_i in the signal list, in simulation |
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2020-05-25 |
Luke Kenneth... | mention zeroing |
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2020-05-25 |
Luke Kenneth... | add links to pseudocode |
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2020-05-24 |
Luke Kenneth... | spelling |
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2020-05-24 |
Luke Kenneth... | spelling |
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2020-05-24 |
Luke Kenneth... | add comments for SPR pipe_data |
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2020-05-24 |
Luke Kenneth... | add SPR pipe_data.py |
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2020-05-24 |
Luke Kenneth... | over 80 char limit |
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2020-05-24 |
Luke Kenneth... | add test of reg output, for MFCRF and ISEL |
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2020-05-24 |
Cesar Strauss | Avoid overwriting the first vcd file with the second one |
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2020-05-24 |
Cesar Strauss | Rename the internal DFF of latchregisters to avoid... |
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2020-05-24 |
Luke Kenneth... | add gitignore for branch fu formal |
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2020-05-24 |
Luke Kenneth... | add OP_CMPB formal proof |
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2020-05-24 |
Michael Nolan | Assert that ctr is only written when needed |
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2020-05-24 |
Luke Kenneth... | split out Popcount into separate module: visually it... |
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2020-05-24 |
Luke Kenneth... | copy code for MTMSR from microwatt into comments |
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2020-05-24 |
Luke Kenneth... | add links for trap main stage |
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2020-05-24 |
Luke Kenneth... | add untested OP_MTMSR and OP_MFMSR |
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2020-05-24 |
Luke Kenneth... | update to new CSV files in submodule |
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2020-05-24 |
Luke Kenneth... | add MFMSR and MTMSRD enums to Function |
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2020-05-24 |
Luke Kenneth... | comment and add links to branch formal proof |
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2020-05-24 |
Luke Kenneth... | add copy of bpermd proof to logical formal proof (not... |
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2020-05-24 |
Luke Kenneth... | track down overwrite of variable b |
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2020-05-24 |
Michael Nolan | Fix proof of bpermd module |
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2020-05-24 |
Michael Nolan | Fix bpermd and make tests pass |
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2020-05-24 |
Michael Nolan | Fix test_pipe_caller to conform to new Data() interface... |
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2020-05-24 |
Luke Kenneth... | add stub regfiles.py |
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2020-05-24 |
Luke Kenneth... | hmm... |
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2020-05-24 |
Luke Kenneth... | add very rapid DummyALU for test purposes in MultiCompUnit |
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2020-05-24 |
Luke Kenneth... | comments on branch pipeline |
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2020-05-24 |
Luke Kenneth... | convert CR pipeline to Data.ok |
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2020-05-24 |
Luke Kenneth... | convert ALU to output Data on int reg |
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2020-05-24 |
Luke Kenneth... | convert logical to output Data on int reg |
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2020-05-24 |
Luke Kenneth... | start using Data in pipelines |
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2020-05-24 |
Luke Kenneth... | cleanup/code-munge on ALU main stage proof |
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2020-05-24 |
Luke Kenneth... | error in alu output stage formal proof setup |
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2020-05-24 |
Luke Kenneth... | output registers need to be Data type (consistently) |
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2020-05-24 |
Luke Kenneth... | spelling mistake in variable |
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2020-05-24 |
Luke Kenneth... | TODO mention OP_MTMSR/OP_MFMSR |
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2020-05-24 |
Luke Kenneth... | add RA to trap pipeline, for OP_MTMSR/OP_MFMSR |
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2020-05-24 |
Luke Kenneth... | move docstring to wiki for compunit |
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2020-05-23 |
colepoirier | Added branch and shift_rot imports to fu/compunits... |
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2020-05-23 |
Cesar Strauss | Add a few test cases with zero_a set, in combination... |
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2020-05-23 |
Cesar Strauss | Allow zero_a to be set when simulating an operation |
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2020-05-23 |
Luke Kenneth... | add input / output stage missing modules |
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2020-05-23 |
Luke Kenneth... | common function for op zero and op immed |
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2020-05-23 |
Cesar Strauss | Choose between RA (src1) and zero immediate, conditione... |
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2020-05-23 |
Luke Kenneth... | update docs on compunits |
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2020-05-23 |
Luke Kenneth... | remove extraneous test_isel |
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2020-05-23 |
Luke Kenneth... | add comments |
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2020-05-23 |
Luke Kenneth... | document purpose of regspec module |
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2020-05-23 |
Luke Kenneth... | split out RegSpecs into separate module |
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2020-05-23 |
Luke Kenneth... | add TODO on multi-in multi-out Function Units |
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2020-05-23 |
Luke Kenneth... | split out RegSpec API into separate class (TODO: move... |
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2020-05-23 |
Luke Kenneth... | add notes on FunctionUnit API |
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2020-05-23 |
Luke Kenneth... | make MultiCompUnit and testing ALU use regspec API... |
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2020-05-23 |
Luke Kenneth... | remove unneeded imports |
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2020-05-23 |
Luke Kenneth... | make demo/test ALU look like nmigen pipeline API |
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2020-05-23 |
Luke Kenneth... | add stub DataMerger class |
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2020-05-23 |
Luke Kenneth... | add link to regspecs on wiki |
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2020-05-23 |
Luke Kenneth... | add regspec capability to MultiCompUnit |
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2020-05-23 |
Michael Nolan | Modify proof of isel to use full CR register |
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2020-05-23 |
Michael Nolan | Add test_isel |
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2020-05-23 |
Luke Kenneth... | make immediate-or-RA selection optional based on awaren... |
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2020-05-23 |
Luke Kenneth... | start to morph MultiCompUnit to take "regspec" as the... |
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2020-05-23 |
Luke Kenneth... | add CR_ISEL formal proof to CR pipeline |
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2020-05-23 |
Luke Kenneth... | add CR_ISEL (and unit test) to CR pipeline |
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2020-05-23 |
Luke Kenneth... | update to (corrected) csv files for CR_ISEL |
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2020-05-23 |
Luke Kenneth... | select bits 2:5 from BC to get CR0 to 7 in DecodeCRin |
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2020-05-23 |
Luke Kenneth... | add gitignore |
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2020-05-23 |
Luke Kenneth... | CR field on Br input data is specd as 0:3 range |
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2020-05-23 |
Luke Kenneth... | add b to CR pipe input data, for isel |
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2020-05-22 |
Luke Kenneth... | add TODO and link to SHIFT_ROT formal bugreport |
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2020-05-22 |
Luke Kenneth... | remove xer.so from ShiftRot formal proof |
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2020-05-22 |
Luke Kenneth... | remove sticky overflow from Shift Rot pipeline |
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2020-05-22 |
Luke Kenneth... | test branch ctr ok flag |
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2020-05-22 |
Luke Kenneth... | cleaner way to test link register ok |
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2020-05-22 |
Luke Kenneth... | whitespace |
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2020-05-22 |
Michael Nolan | Fix link handling in branch proof |
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2020-05-22 |
Michael Nolan | Update to latest wiki version - fix cr0 input for OP_CNTZ |
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2020-05-22 |
Luke Kenneth... | variable-name munging for branch formal |
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2020-05-22 |
Michael Nolan | Add formal proof for branch unit, fix bug with bcreg |
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2020-05-22 |
Luke Kenneth... | cleanup logical pipe formal proof |
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2020-05-22 |
Luke Kenneth... | split out Logical Input and Output stages to common... |
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2020-05-22 |
Luke Kenneth... | div probably uses ALU not Logical, needs double-checkin... |
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2020-05-22 |
Luke Kenneth... | update comments for ALUCompUnit |
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2020-05-22 |
Luke Kenneth... | soc.fu.logical.input_stage no different from ALU: delete |
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2020-05-22 |
Luke Kenneth... | covert ALU FU to CommonInputStage |
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2020-05-22 |
Luke Kenneth... | create common input pipe spec to avoid code-duplication |
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