2021-11-25 |
Tobias Platen | add testcase for invalid pagetable |
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2021-11-25 |
Tobias Platen | pimem: reset on exception |
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2021-11-25 |
Tobias Platen | remove unuses dsisr signal |
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2021-11-25 |
Tobias Platen | reset state to idle on exception |
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2021-11-25 |
Luke Kenneth... | more sorting scoremulti |
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2021-11-25 |
Luke Kenneth... | more sorting out scoremulti |
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2021-11-25 |
Luke Kenneth... | add test pspec for scoremulti to work |
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2021-11-24 |
Luke Kenneth... | convert hazard bitvectors to Reset-Priority SRLatch... |
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2021-11-24 |
Tobias Platen | fix exception handling in pi_ld |
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2021-11-24 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-24 |
Tobias Platen | improve debug output in mmu.py |
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2021-11-24 |
Luke Kenneth... | fix write-after-write hazard detection |
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2021-11-24 |
Luke Kenneth... | when allow_overlap enabled do a manual wait until all... |
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2021-11-24 |
Luke Kenneth... | code-comments |
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2021-11-24 |
Luke Kenneth... | add write-after-write hazard detection |
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2021-11-24 |
Luke Kenneth... | add 2nd hazard bitvector port for write-after-write |
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2021-11-24 |
Luke Kenneth... | whoops merged the two write-ports for RT and RA-with... |
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2021-11-24 |
Luke Kenneth... | disable hazard vectors when overlap is not requested... |
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2021-11-23 |
Luke Kenneth... | update submodules |
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2021-11-23 |
Luke Kenneth... | more comments |
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2021-11-23 |
Tobias Platen | pimem changes for st exception handling |
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2021-11-23 |
Tobias Platen | fix test_loadstore1.py |
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2021-11-23 |
Luke Kenneth... | add FU write-after-write hazard detection Signal (dummy... |
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2021-11-23 |
Luke Kenneth... | add code-comments, link to in-order core |
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2021-11-23 |
Luke Kenneth... | more use of namedtuples in core.py for clarity |
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2021-11-23 |
Luke Kenneth... | start some use of namedtuples in core.py |
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2021-11-23 |
Luke Kenneth... | use some namedtuples to make things clearer in core.py |
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2021-11-23 |
Luke Kenneth... | use fascinating trick of defaultdict-of-defaultdicts |
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2021-11-22 |
Tobias Platen | add store testcase |
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2021-11-22 |
Tobias Platen | fix fast exception handling for pi_st |
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2021-11-22 |
Luke Kenneth... | make FetchFSM take PC as an input in its ispec |
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2021-11-22 |
Luke Kenneth... | local variable rename in FetchFSM |
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2021-11-22 |
Luke Kenneth... | split out FetchFSM into separate module |
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2021-11-22 |
Luke Kenneth... | whoops accidentally committed commented-out test for... |
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2021-11-21 |
Luke Kenneth... | reset execute back to ISSUE_START if at INSN_WAIT and |
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2021-11-21 |
Luke Kenneth... | restrict (refine) hazard selection to the one being... |
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2021-11-21 |
Luke Kenneth... | block picker hazard on input to PriorityPicker rather... |
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2021-11-21 |
Luke Kenneth... | parse test_issuer args allow option "allow-overlap... |
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2021-11-21 |
Luke Kenneth... | complex. TestRunner now does not work properly unless... |
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2021-11-21 |
Luke Kenneth... | fixed issue with hazard dependencies, read will nott |
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2021-11-21 |
Tobias Platen | add testcase for fast exceptions on store |
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2021-11-20 |
Tobias Platen | fix pi_ld testcase |
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2021-11-19 |
Luke Kenneth... | add both bitdict and selected args to connect_rd/wrport |
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2021-11-19 |
Luke Kenneth... | sorting out issue hazard conflicts in core. |
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2021-11-19 |
Luke Kenneth... | debug and cleanup |
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2021-11-19 |
Luke Kenneth... | rename instruction_active to instr_active in core |
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2021-11-19 |
Luke Kenneth... | read latch on regfile ports was fine, the combinatorial... |
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2021-11-19 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-19 |
Luke Kenneth... | latch copy of read register numbers, not in use due... |
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2021-11-19 |
Luke Kenneth... | use read spec in connect_rdport rather than list of... |
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2021-11-19 |
Luke Kenneth... | capture write regfile numbers into write latches in... |
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2021-11-19 |
Luke Kenneth... | code tidyup / comments, and use defaultdict |
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2021-11-19 |
Luke Kenneth... | create lists of latches in each FU, to record the read... |
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2021-11-19 |
Luke Kenneth... | for some reason DMI CTRL returns status of 0x6 not 0x0 |
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2021-11-19 |
Luke Kenneth... | missing argument, domain="sync" in JTAG instance |
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2021-11-19 |
Luke Kenneth... | return None if data returned is empty |
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2021-11-18 |
Luke Kenneth... | remove combinatorial loop in core instruction conflict... |
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2021-11-18 |
Luke Kenneth... | experimenting with overlapping instructions, bit of... |
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2021-11-18 |
Luke Kenneth... | set up core processing FSM, which captures data if... |
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2021-11-18 |
Luke Kenneth... | set up a temporary copy of CoreInput |
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2021-11-18 |
Luke Kenneth... | experiment allowing overlap (activated with --allow... |
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2021-11-18 |
Luke Kenneth... | remove unneeded import |
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2021-11-18 |
Tobias Platen | more work on test_loadstore1 |
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2021-11-17 |
Jacob Lifshay | start adding bitmanip FU |
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2021-11-17 |
Tobias Platen | PortInterfaceBase: fix fast exception handling |
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2021-11-17 |
Tobias Platen | whitespace |
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2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-17 |
Tobias Platen | fix mistake in test_pi2ls.py |
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2021-11-17 |
Luke Kenneth... | reading of regfile bitvector added, which activates... |
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2021-11-17 |
Luke Kenneth... | core hazard bitvector regfiles need to be readable |
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2021-11-17 |
Tobias Platen | fixed busy waiting in pi_st |
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2021-11-17 |
Luke Kenneth... | add option to test_issuer.py to allow for overlapping... |
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2021-11-17 |
Luke Kenneth... | add ability to run hazard instruction for test purposes |
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2021-11-17 |
Luke Kenneth... | detect the case in Core bitvector when the Function... |
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2021-11-17 |
Luke Kenneth... | add probe of whether CompUnit ALU is done or not. |
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2021-11-17 |
Luke Kenneth... | missing optional check on make_hazard_vecs |
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2021-11-17 |
Luke Kenneth... | move core hazard set/clear to separate function, for... |
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2021-11-17 |
Luke Kenneth... | whoops context-indentation by mistake (no harm done... |
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2021-11-17 |
Luke Kenneth... | add a FetchOutput pipeline data structure |
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2021-11-16 |
Luke Kenneth... | print out regfile unary status, bit of name-cleanup |
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2021-11-16 |
Luke Kenneth... | use a virtual regfile port for the hazard bitvectors |
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2021-11-16 |
Tobias Platen | pi_ld busy waiting fix |
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2021-11-16 |
Tobias Platen | loadstore1 now reports exception reason |
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2021-11-16 |
Luke Kenneth... | create set/get ports for bitvectors |
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2021-11-16 |
Luke Kenneth... | capture write port (wrflag) in byregfiles_spec for... |
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2021-11-16 |
Luke Kenneth... | rename regports for bitvectors so that |
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2021-11-16 |
Luke Kenneth... | starting to get write-clear of hazard vectors operating |
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2021-11-16 |
Luke Kenneth... | whoops, hazard vectors were depth 1 width N |
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2021-11-15 |
Tobias Platen | report dar on exception + test case |
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2021-11-15 |
Tobias Platen | add test_loadstore1.py |
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2021-11-13 |
Luke Kenneth... | add quick instructions on how to run pinouts.py to... |
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2021-11-13 |
Luke Kenneth... | update submodule to make ngi pointer router pinouts |
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2021-11-13 |
Luke Kenneth... | add new get_pinspec_resources function which creates... |
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2021-11-13 |
Luke Kenneth... | code-comment for get_pinspecs() |
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2021-11-13 |
Luke Kenneth... | start adding hazard vector setting in core (unfinished) |
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2021-11-11 |
Luke Kenneth... | debug prints |
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2021-11-11 |
Luke Kenneth... | fix regfile port names for "fast" port access (regreduc... |
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2021-11-11 |
Luke Kenneth... | TODO, implement is_dcbz |
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2021-11-11 |
Luke Kenneth... | code-comments |
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2021-11-11 |
Luke Kenneth... | split out core input/output into separate file core_data.py |
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