soc.git
2021-11-25 Tobias Platenadd testcase for invalid pagetable
2021-11-25 Tobias Platenpimem: reset on exception
2021-11-25 Tobias Platenremove unuses dsisr signal
2021-11-25 Tobias Platenreset state to idle on exception
2021-11-25 Luke Kenneth... more sorting scoremulti
2021-11-25 Luke Kenneth... more sorting out scoremulti
2021-11-25 Luke Kenneth... add test pspec for scoremulti to work
2021-11-24 Luke Kenneth... convert hazard bitvectors to Reset-Priority SRLatch...
2021-11-24 Tobias Platenfix exception handling in pi_ld
2021-11-24 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-24 Tobias Platenimprove debug output in mmu.py
2021-11-24 Luke Kenneth... fix write-after-write hazard detection
2021-11-24 Luke Kenneth... when allow_overlap enabled do a manual wait until all...
2021-11-24 Luke Kenneth... code-comments
2021-11-24 Luke Kenneth... add write-after-write hazard detection
2021-11-24 Luke Kenneth... add 2nd hazard bitvector port for write-after-write
2021-11-24 Luke Kenneth... whoops merged the two write-ports for RT and RA-with...
2021-11-24 Luke Kenneth... disable hazard vectors when overlap is not requested...
2021-11-23 Luke Kenneth... update submodules
2021-11-23 Luke Kenneth... more comments
2021-11-23 Tobias Platenpimem changes for st exception handling
2021-11-23 Tobias Platenfix test_loadstore1.py
2021-11-23 Luke Kenneth... add FU write-after-write hazard detection Signal (dummy...
2021-11-23 Luke Kenneth... add code-comments, link to in-order core
2021-11-23 Luke Kenneth... more use of namedtuples in core.py for clarity
2021-11-23 Luke Kenneth... start some use of namedtuples in core.py
2021-11-23 Luke Kenneth... use some namedtuples to make things clearer in core.py
2021-11-23 Luke Kenneth... use fascinating trick of defaultdict-of-defaultdicts
2021-11-22 Tobias Platenadd store testcase
2021-11-22 Tobias Platenfix fast exception handling for pi_st
2021-11-22 Luke Kenneth... make FetchFSM take PC as an input in its ispec
2021-11-22 Luke Kenneth... local variable rename in FetchFSM
2021-11-22 Luke Kenneth... split out FetchFSM into separate module
2021-11-22 Luke Kenneth... whoops accidentally committed commented-out test for...
2021-11-21 Luke Kenneth... reset execute back to ISSUE_START if at INSN_WAIT and
2021-11-21 Luke Kenneth... restrict (refine) hazard selection to the one being...
2021-11-21 Luke Kenneth... block picker hazard on input to PriorityPicker rather...
2021-11-21 Luke Kenneth... parse test_issuer args allow option "allow-overlap...
2021-11-21 Luke Kenneth... complex. TestRunner now does not work properly unless...
2021-11-21 Luke Kenneth... fixed issue with hazard dependencies, read will nott
2021-11-21 Tobias Platenadd testcase for fast exceptions on store
2021-11-20 Tobias Platenfix pi_ld testcase
2021-11-19 Luke Kenneth... add both bitdict and selected args to connect_rd/wrport
2021-11-19 Luke Kenneth... sorting out issue hazard conflicts in core.
2021-11-19 Luke Kenneth... debug and cleanup
2021-11-19 Luke Kenneth... rename instruction_active to instr_active in core
2021-11-19 Luke Kenneth... read latch on regfile ports was fine, the combinatorial...
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth... latch copy of read register numbers, not in use due...
2021-11-19 Luke Kenneth... use read spec in connect_rdport rather than list of...
2021-11-19 Luke Kenneth... capture write regfile numbers into write latches in...
2021-11-19 Luke Kenneth... code tidyup / comments, and use defaultdict
2021-11-19 Luke Kenneth... create lists of latches in each FU, to record the read...
2021-11-19 Luke Kenneth... for some reason DMI CTRL returns status of 0x6 not 0x0
2021-11-19 Luke Kenneth... missing argument, domain="sync" in JTAG instance
2021-11-19 Luke Kenneth... return None if data returned is empty
2021-11-18 Luke Kenneth... remove combinatorial loop in core instruction conflict...
2021-11-18 Luke Kenneth... experimenting with overlapping instructions, bit of...
2021-11-18 Luke Kenneth... set up core processing FSM, which captures data if...
2021-11-18 Luke Kenneth... set up a temporary copy of CoreInput
2021-11-18 Luke Kenneth... experiment allowing overlap (activated with --allow...
2021-11-18 Luke Kenneth... remove unneeded import
2021-11-18 Tobias Platenmore work on test_loadstore1
2021-11-17 Jacob Lifshaystart adding bitmanip FU
2021-11-17 Tobias PlatenPortInterfaceBase: fix fast exception handling
2021-11-17 Tobias Platenwhitespace
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Tobias Platenfix mistake in test_pi2ls.py
2021-11-17 Luke Kenneth... reading of regfile bitvector added, which activates...
2021-11-17 Luke Kenneth... core hazard bitvector regfiles need to be readable
2021-11-17 Tobias Platenfixed busy waiting in pi_st
2021-11-17 Luke Kenneth... add option to test_issuer.py to allow for overlapping...
2021-11-17 Luke Kenneth... add ability to run hazard instruction for test purposes
2021-11-17 Luke Kenneth... detect the case in Core bitvector when the Function...
2021-11-17 Luke Kenneth... add probe of whether CompUnit ALU is done or not.
2021-11-17 Luke Kenneth... missing optional check on make_hazard_vecs
2021-11-17 Luke Kenneth... move core hazard set/clear to separate function, for...
2021-11-17 Luke Kenneth... whoops context-indentation by mistake (no harm done...
2021-11-17 Luke Kenneth... add a FetchOutput pipeline data structure
2021-11-16 Luke Kenneth... print out regfile unary status, bit of name-cleanup
2021-11-16 Luke Kenneth... use a virtual regfile port for the hazard bitvectors
2021-11-16 Tobias Platenpi_ld busy waiting fix
2021-11-16 Tobias Platenloadstore1 now reports exception reason
2021-11-16 Luke Kenneth... create set/get ports for bitvectors
2021-11-16 Luke Kenneth... capture write port (wrflag) in byregfiles_spec for...
2021-11-16 Luke Kenneth... rename regports for bitvectors so that
2021-11-16 Luke Kenneth... starting to get write-clear of hazard vectors operating
2021-11-16 Luke Kenneth... whoops, hazard vectors were depth 1 width N
2021-11-15 Tobias Platenreport dar on exception + test case
2021-11-15 Tobias Platenadd test_loadstore1.py
2021-11-13 Luke Kenneth... add quick instructions on how to run pinouts.py to...
2021-11-13 Luke Kenneth... update submodule to make ngi pointer router pinouts
2021-11-13 Luke Kenneth... add new get_pinspec_resources function which creates...
2021-11-13 Luke Kenneth... code-comment for get_pinspecs()
2021-11-13 Luke Kenneth... start adding hazard vector setting in core (unfinished)
2021-11-11 Luke Kenneth... debug prints
2021-11-11 Luke Kenneth... fix regfile port names for "fast" port access (regreduc...
2021-11-11 Luke Kenneth... TODO, implement is_dcbz
2021-11-11 Luke Kenneth... code-comments
2021-11-11 Luke Kenneth... split out core input/output into separate file core_data.py
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