2020-08-24 |
Luke Kenneth... | make it easier to select FSM/Pipe DIV unit |
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2020-08-24 |
Luke Kenneth... | fix *another* ld-update-related timing / FSM issue |
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2020-08-24 |
Luke Kenneth... | tidyup / shuffle after review |
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2020-08-24 |
Luke Kenneth... | remove default parameter |
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2020-08-24 |
Luke Kenneth... | "WAY" does not exist - range(NUM_WAYS) was intended |
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2020-08-24 |
Luke Kenneth... | use WAY_BITS in appropriate locations |
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2020-08-24 |
Luke Kenneth... | reminder that the license (reflecting what is in setup... |
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2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-24 |
Cole Poirier | dcache.py commit first full tranlation pass, about... |
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2020-08-23 |
Luke Kenneth... | update copyright notices to include additional primary... |
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2020-08-23 |
Luke Kenneth... | add load algebraic immediate unit test |
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2020-08-23 |
Luke Kenneth... | add algebraic ld tests lwax, lwaux |
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2020-08-23 |
Michael Nolan | Add copyright to files I primarily authored in simulator/ |
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2020-08-23 |
Michael Nolan | Add copyright to files in fu/ that I was the primary... |
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2020-08-23 |
Michael Nolan | Add copyright statement to power_decoder.py |
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2020-08-23 |
Luke Kenneth... | bring "core stopped" signal out through DMI interface |
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2020-08-23 |
Luke Kenneth... | add in DMI "stat" loop which monitors core "stopping" |
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2020-08-23 |
Cesar Strauss | Allow an empty style, and passing default styles as... |
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2020-08-23 |
Cesar Strauss | Add comment node type |
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2020-08-23 |
Cesar Strauss | Add base and display styles |
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2020-08-23 |
Cesar Strauss | Apply style from node own name |
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2020-08-23 |
Cesar Strauss | Add color style |
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2020-08-23 |
Cesar Strauss | Collect styles from the tuple |
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2020-08-23 |
Cesar Strauss | Propagate the root style to all signals |
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2020-08-23 |
Luke Kenneth... | comment why litex sim mem map is altered |
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2020-08-23 |
Luke Kenneth... | multiply does not have invert_in, zero_a or invert_out |
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2020-08-22 |
Luke Kenneth... | rename invert_a to invert_in because logical inverts RB |
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2020-08-22 |
Luke Kenneth... | update submodule |
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2020-08-22 |
Luke Kenneth... | load bios not 1.bin unit test |
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2020-08-22 |
Luke Kenneth... | add extra div regression tests |
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2020-08-22 |
Cesar Strauss | Move comments to the docstring |
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2020-08-22 |
Cesar Strauss | Walk the DOM and emit the trace names |
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2020-08-22 |
Luke Kenneth... | add eqv to logical unit test |
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2020-08-22 |
Luke Kenneth... | add nor and nand to unit test |
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2020-08-22 |
Luke Kenneth... | moved to div pipe temporarily in compunits |
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2020-08-22 |
Luke Kenneth... | bug in andc and orc, complement was taking place on... |
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2020-08-22 |
Luke Kenneth... | extend addis test |
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2020-08-22 |
Luke Kenneth... | add andc and orc tests, failing because RB needs invers... |
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2020-08-22 |
Luke Kenneth... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-22 |
Cesar Strauss | First draft of a mini-language to describe GTKWave... |
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2020-08-22 |
Luke Kenneth... | submodule update |
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2020-08-22 |
Luke Kenneth... | add regression test for nonzero addis |
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2020-08-22 |
Luke Kenneth... | add means to run microwatt test binaries |
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2020-08-22 |
Luke Kenneth... | r0 zero tests on addis, fails |
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2020-08-22 |
Luke Kenneth... | investigating litex sdrinit function |
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2020-08-22 |
Luke Kenneth... | add pseudo-op conversion |
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2020-08-22 |
Luke Kenneth... | add start of litex bios counter loop |
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2020-08-21 |
Luke Kenneth... | remove extraneous comments |
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2020-08-21 |
Luke Kenneth... | testing 64-bit wishbone bus after 32-bit *still* fails... |
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2020-08-21 |
Tobias Platen | typo fix in test_l0_cache_buffer2.py |
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2020-08-21 |
Cole Poirier | dcache.py fix asserts, use backslash and two strings... |
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2020-08-21 |
Cole Poirier | dcache.py replace functions that return signals with... |
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2020-08-21 |
Cole Poirier | wb_types fix typo |
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2020-08-21 |
Tobias Platen | connect TestCachedMemoryPortInterface to LDSTSplitter |
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2020-08-21 |
Luke Kenneth... | get litex sim enabled with 32-bit wishbone bus |
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2020-08-21 |
Luke Kenneth... | ld/st bus reduction test operational |
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2020-08-21 |
Luke Kenneth... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth... | add in WishboneDownConvert into LoadStoreUnitInterface |
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2020-08-21 |
Luke Kenneth... | comment formatting |
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2020-08-21 |
Luke Kenneth... | remove default values |
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2020-08-21 |
Luke Kenneth... | just range(the_constant) |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline WIP: mullw and mullwu covered. |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline: account for overflow flags. WIP |
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2020-08-21 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-21 |
Cole Poirier | dcache.py commit today and yesterday's progress (sorry... |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline proofs: mulli / mullw WIP. |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: muldw(u) |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: signed mulhw |
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2020-08-20 |
Tobias Platen | start wiring TestCachedMemoryPortInterface |
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2020-08-20 |
Tobias Platen | testcase refactoring |
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2020-08-20 |
Tobias Platen | add new class TestCachedMemoryPortInterface |
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2020-08-20 |
Luke Kenneth... | bugfix wishbone downconvert using wb sram 64-to-32... |
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2020-08-20 |
Luke Kenneth... | add a wishbone upconverter |
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2020-08-19 |
Luke Kenneth... | rename and document fields in shift_rot proof |
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2020-08-19 |
Luke Kenneth... | comments in dcache |
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2020-08-19 |
Luke Kenneth... | more subtle interactions between wishbone bus when... |
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2020-08-19 |
Luke Kenneth... | bit of a reorg of mul proof, tracking down missing |
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2020-08-19 |
Luke Kenneth... | move long mul tests to separate unit test |
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2020-08-19 |
Luke Kenneth... | use "Mask" class which is more gate-efficient than... |
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2020-08-19 |
Samuel A. Falvo II | WIP: OP_MUL proofs started. |
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2020-08-19 |
Luke Kenneth... | set up StageChain of 3 mul stages |
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2020-08-18 |
Cole Poirier | fu/mul/test/test_pipe_caller.py test case_all_rb_close_... |
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2020-08-18 |
Tobias Platen | add testcase for LDSTSplitter using PortInterface |
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2020-08-18 |
Luke Kenneth... | fix spr state test |
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2020-08-18 |
Luke Kenneth... | add comment in dcache.py |
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2020-08-17 |
Cole Poirier | dcache.py commit today's progress on translating dcache... |
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2020-08-17 |
Cole Poirier | Create file experiment/wb_types.py to mirror microwatt... |
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2020-08-17 |
Luke Kenneth... | move Mask to nmutil |
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2020-08-17 |
Luke Kenneth... | turn SelectableInt less/greater into signed versions. |
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2020-08-17 |
Luke Kenneth... | use longer memtest in litex sim |
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2020-08-17 |
Luke Kenneth... | adjust litex bios cmp test |
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2020-08-17 |
Luke Kenneth... | fix signed variants of cmp in alu |
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2020-08-17 |
Luke Kenneth... | add new cmp test for alu |
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2020-08-17 |
Luke Kenneth... | use shift module in mmu. to be moved to nmutil |
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2020-08-16 |
Cole Poirier | mmu.py fix formatting 80 char limit |
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2020-08-16 |
Luke Kenneth... | attempting to track down bug in litex bios memtest |
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2020-08-16 |
Luke Kenneth... | read delay on getting regfile data |
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2020-08-16 |
Luke Kenneth... | limit debug reporting in litex sim to range of pc |
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2020-08-16 |
Luke Kenneth... | cmp test from litex bios |
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next |