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soc.git
2022-04-27 Jacob Lifshayswitch cached-property dependency to using libre-soc... commit | commitdiff | tree
2022-04-27 Jacob Lifshayimproved goldschmidt division algorithm parameter optim... commit | commitdiff | tree
2022-04-27 Jacob Lifshaysplit out non-derived params into separate class withou... commit | commitdiff | tree
2022-04-27 Jacob Lifshaysplit out n_hat as separate property commit | commitdiff | tree
2022-04-27 Jacob Lifshayadd default_cost_fn commit | commitdiff | tree
2022-04-27 Jacob Lifshaymove GoldschmidtDivParams.get to bottom of class commit | commitdiff | tree
2022-04-27 Jacob Lifshayrename _goldschmidt_div_ops to GoldschmidtDivState... commit | commitdiff | tree
2022-04-26 Jacob Lifshaygoldschmidt division works! still needs better paramete... commit | commitdiff | tree
2022-04-26 Jacob Lifshayfix goofed __init__.py file name commit | commitdiff | tree
2022-04-25 Jacob Lifshayworking on goldschmidt_div_sqrt.py commit | commitdiff | tree
2022-04-25 Jacob Lifshayadd cached_property dependency commit | commitdiff | tree
2022-04-23 Jacob Lifshayworking on goldschmidt division algorithm commit | commitdiff | tree
2022-04-22 Luke Kenneth... whitespace commit | commitdiff | tree
2022-04-22 Jacob Lifshayadd WIP goldschmidt division algorithm commit | commitdiff | tree
2022-04-17 Cesar StraussImplement a 1W/1R register file, XOR style commit | commitdiff | tree
2022-04-17 Cesar StraussFormal proof of pseudo 1W/2R SRAM commit | commitdiff | tree
2022-04-17 Cesar StraussAdd transparent option for the full read port commit | commitdiff | tree
2022-04-17 Cesar StraussImplement a pseudo 1W/2R memory commit | commitdiff | tree
2022-04-16 Luke Kenneth... reduce dcache/icache number of ways, to fit into ECP5... commit | commitdiff | tree
2022-04-16 Tobias Platenpart two of issuer_fix: read pspec.microwatt_old and... commit | commitdiff | tree
2022-04-16 Cesar StraussCheck non-transparent 1W/1R SRAM wrapper commit | commitdiff | tree
2022-04-16 Cesar StraussEnable read port for non-transparent memories commit | commitdiff | tree
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc commit | commitdiff | tree
2022-04-16 Tobias Platenpart one of issuer_fix: add parameter to issuer_verilog.py commit | commitdiff | tree
2022-04-16 Cesar StraussAdd port declarations to the SRAM wrappers commit | commitdiff | tree
2022-04-16 Cesar StraussChange write lane signal from one-hot to binary commit | commitdiff | tree
2022-04-16 Luke Kenneth... whoops, WBASyncBridge ack signal not wired up! commit | commitdiff | tree
2022-04-16 Luke Kenneth... select width is data_width // data granularity. commit | commitdiff | tree
2022-04-16 Cesar StraussSynchronize LVT state, completing the induction proof commit | commitdiff | tree
2022-04-16 Cesar StraussSync proof state with downstream memories commit | commitdiff | tree
2022-04-16 Luke Kenneth... put the old microwatt compatibility back commit | commitdiff | tree
2022-04-16 Luke Kenneth... blegh. commit | commitdiff | tree
2022-04-15 Cesar StraussComplete moving the induction support into the DUT commit | commitdiff | tree
2022-04-15 Cesar StraussFix incorrect signal widths commit | commitdiff | tree
2022-04-15 Cesar StraussMove part of formal proof to the implementation commit | commitdiff | tree
2022-04-14 Luke Kenneth... add option Spec to XICS ICP/ICS to be able to activate... commit | commitdiff | tree
2022-04-14 Luke Kenneth... move IRQLine out because that makes soc dependent on... commit | commitdiff | tree
2022-04-14 Luke Kenneth... 80 char limit, remove creation of stall from ack/cyc... commit | commitdiff | tree
2022-04-14 Raptor Engineering... wb_async: Allow different feature fields for master... commit | commitdiff | tree
2022-04-14 Raptor Engineering... Add separate memory clock register to SYSCON commit | commitdiff | tree
2022-04-12 Tobias Platenissuer.py: add microwatt_old and microwatt_debug options commit | commitdiff | tree
2022-04-11 Raptor Engineering... Separate core and nest clocks in Microwatt SYSCON commit | commitdiff | tree
2022-04-11 Raptor Engineering... Add initial wrapper for Wishbone asynchronous bridge... commit | commitdiff | tree
2022-04-10 Cesar StraussBegin a formal proof of the LVT-based 1W/1R wrapper commit | commitdiff | tree
2022-04-10 Cesar StraussImplement 1W/1R with a transparent (or not) read port. commit | commitdiff | tree
2022-04-10 Cesar StraussImplement a true 1W/1R memory from 1RW blocks commit | commitdiff | tree
2022-04-09 Luke Kenneth... add a new make target for setting coldboot firmware... commit | commitdiff | tree
2022-04-08 Luke Kenneth... syntax error commit | commitdiff | tree
2022-04-08 Luke Kenneth... add dram to SysCon commit | commitdiff | tree
2022-04-08 Luke Kenneth... add SPI offset to microwatt syscon commit | commitdiff | tree
2022-04-06 Luke Kenneth... only add clock-settings on ECP5 due to special SPI... commit | commitdiff | tree
2022-04-04 Luke Kenneth... add tempfile to uart16550 wrapper which defines DATA_BU... commit | commitdiff | tree
2022-04-04 Luke Kenneth... disable sphinx verilg-diagrams for now commit | commitdiff | tree
2022-04-04 Luke Kenneth... allow direction-setting on each of dq0-3 in Tercel... commit | commitdiff | tree
2022-04-03 Luke Kenneth... cant stand the practice of putting docstrings *after... commit | commitdiff | tree
2022-04-03 Cesar StraussExtend the proof to a non-transparent port commit | commitdiff | tree
2022-04-03 Cesar StraussRun formal proof on both types (even/odd) of phased... commit | commitdiff | tree
2022-04-03 Cesar StraussComplete the formal proof of the pseudo dual port SRAM commit | commitdiff | tree
2022-04-03 Cesar StraussImplement a debug port on the pseudo 1W/1R SRAM commit | commitdiff | tree
2022-04-03 Cesar StraussFormal proof of the phased write dual port memory wrapper commit | commitdiff | tree
2022-04-03 Luke Kenneth... correct default to zero string not zero int commit | commitdiff | tree
2022-04-03 Luke Kenneth... add alternative pc_reset argument to issuer_verilog.py commit | commitdiff | tree
2022-04-03 Luke Kenneth... fix some of instantiation errors in opencores_ethmac.py commit | commitdiff | tree
2022-04-02 Raptor Engineering... Fix opencores EthMAC module wiring commit | commitdiff | tree
2022-04-02 Cesar StraussImplement transparent read ports on the phased write... commit | commitdiff | tree
2022-04-02 Cesar StraussImplement and test a "phased write port" memory commit | commitdiff | tree
2022-03-31 Luke Kenneth... invert cs_n pin in Tercel commit | commitdiff | tree
2022-03-30 Luke Kenneth... nope, default features in Tercel WB Buses need to not... commit | commitdiff | tree
2022-03-29 Luke Kenneth... add bus.err to list of default Wishbone signals in... commit | commitdiff | tree
2022-03-29 Luke Kenneth... byte-reverse Tercel read/write data and config bus... commit | commitdiff | tree
2022-03-29 Luke Kenneth... set clock freq Constant length to 32-bit in Tercel. commit | commitdiff | tree
2022-03-29 Luke Kenneth... self.specials does not exist, Instances must be added... commit | commitdiff | tree
2022-03-29 Luke Kenneth... more sorting out wishbone names in Tercel commit | commitdiff | tree
2022-03-29 Luke Kenneth... fix names of Instance signals in Tercel commit | commitdiff | tree
2022-03-29 Luke Kenneth... sort out variable names in Tercel commit | commitdiff | tree
2022-03-29 Luke Kenneth... self.comb does not exist, comb is a local temp-var... commit | commitdiff | tree
2022-03-29 Luke Kenneth... whitespace cleanup (80 char limit) commit | commitdiff | tree
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC commit | commitdiff | tree
2022-03-27 Cesar StraussFinish the SRAM formal proof by implementing induction commit | commitdiff | tree
2022-03-26 Cesar StraussAdd formal verification of the single port memory block commit | commitdiff | tree
2022-03-26 Luke Kenneth... rename PLRU modules to avoid conflict in microwatt commit | commitdiff | tree
2022-03-18 Luke Kenneth... whitespace cleanup (80 char limit, pep8) commit | commitdiff | tree
2022-03-18 Luke Kenneth... turn CompALU/CompLDST latches synchronous commit | commitdiff | tree
2022-03-16 Raptor Engineering... Add initial Tercel integration commit | commitdiff | tree
2022-03-13 Cesar StraussSimulate some read/write/modify operations on the SRAM... commit | commitdiff | tree
2022-03-13 Cesar StraussAdd a Single R/W Port SRAM model commit | commitdiff | tree
2022-03-12 Luke Kenneth... add extra pipeline stages to ALU FU to make timing commit | commitdiff | tree
2022-03-12 Luke Kenneth... introduce extra register of delay to split combinatoria... commit | commitdiff | tree
2022-03-12 Luke Kenneth... Revert "read last row from r.wb.adr not r.req_adr in... commit | commitdiff | tree
2022-03-12 Luke Kenneth... Revert "store cur_state.pc+4 in separate register to... commit | commitdiff | tree
2022-03-12 Luke Kenneth... store cur_state.pc+4 in separate register to help reduce commit | commitdiff | tree
2022-03-12 Luke Kenneth... read last row from r.wb.adr not r.req_adr in icache commit | commitdiff | tree
2022-03-08 Luke Kenneth... remove stbs_done in icache.py commit | commitdiff | tree
2022-03-08 Luke Kenneth... remove ld_stbs_done from dcache: not needed commit | commitdiff | tree
2022-03-08 Luke Kenneth... work-in-progress on sdram opencores wrapper commit | commitdiff | tree
2022-03-06 Cesar StraussCopy the startup delay from issuer.py to inorder.py commit | commitdiff | tree
2022-02-28 Luke Kenneth... attempting to introduce an extra few clock cycles delay... commit | commitdiff | tree
2022-02-27 Luke Kenneth... for lulz make I-Cache possible to set to 32-bit (XLEN=32) commit | commitdiff | tree
2022-02-27 Luke Kenneth... bit_length is 1 more than needed: subtract 1 from XLEN... commit | commitdiff | tree
2022-02-27 Luke Kenneth... fix up shift_rot test_pipe_caller to new regspeckls... commit | commitdiff | tree
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