2020-08-21 |
Luke Kenneth... | testing 64-bit wishbone bus after 32-bit *still* fails... |
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2020-08-21 |
Tobias Platen | typo fix in test_l0_cache_buffer2.py |
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2020-08-21 |
Cole Poirier | dcache.py fix asserts, use backslash and two strings... |
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2020-08-21 |
Cole Poirier | dcache.py replace functions that return signals with... |
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2020-08-21 |
Cole Poirier | wb_types fix typo |
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2020-08-21 |
Tobias Platen | connect TestCachedMemoryPortInterface to LDSTSplitter |
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2020-08-21 |
Luke Kenneth... | get litex sim enabled with 32-bit wishbone bus |
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2020-08-21 |
Luke Kenneth... | ld/st bus reduction test operational |
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2020-08-21 |
Luke Kenneth... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth... | add in WishboneDownConvert into LoadStoreUnitInterface |
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2020-08-21 |
Luke Kenneth... | comment formatting |
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2020-08-21 |
Luke Kenneth... | remove default values |
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2020-08-21 |
Luke Kenneth... | just range(the_constant) |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline WIP: mullw and mullwu covered. |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline: account for overflow flags. WIP |
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2020-08-21 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-21 |
Cole Poirier | dcache.py commit today and yesterday's progress (sorry... |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline proofs: mulli / mullw WIP. |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: muldw(u) |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: signed mulhw |
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2020-08-20 |
Tobias Platen | start wiring TestCachedMemoryPortInterface |
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2020-08-20 |
Tobias Platen | testcase refactoring |
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2020-08-20 |
Tobias Platen | add new class TestCachedMemoryPortInterface |
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2020-08-20 |
Luke Kenneth... | bugfix wishbone downconvert using wb sram 64-to-32... |
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2020-08-20 |
Luke Kenneth... | add a wishbone upconverter |
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2020-08-19 |
Luke Kenneth... | rename and document fields in shift_rot proof |
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2020-08-19 |
Luke Kenneth... | comments in dcache |
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2020-08-19 |
Luke Kenneth... | more subtle interactions between wishbone bus when... |
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2020-08-19 |
Luke Kenneth... | bit of a reorg of mul proof, tracking down missing |
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2020-08-19 |
Luke Kenneth... | move long mul tests to separate unit test |
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2020-08-19 |
Luke Kenneth... | use "Mask" class which is more gate-efficient than... |
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2020-08-19 |
Samuel A. Falvo II | WIP: OP_MUL proofs started. |
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2020-08-19 |
Luke Kenneth... | set up StageChain of 3 mul stages |
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2020-08-18 |
Cole Poirier | fu/mul/test/test_pipe_caller.py test case_all_rb_close_... |
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2020-08-18 |
Tobias Platen | add testcase for LDSTSplitter using PortInterface |
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2020-08-18 |
Luke Kenneth... | fix spr state test |
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2020-08-18 |
Luke Kenneth... | add comment in dcache.py |
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2020-08-17 |
Cole Poirier | dcache.py commit today's progress on translating dcache... |
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2020-08-17 |
Cole Poirier | Create file experiment/wb_types.py to mirror microwatt... |
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2020-08-17 |
Luke Kenneth... | move Mask to nmutil |
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2020-08-17 |
Luke Kenneth... | turn SelectableInt less/greater into signed versions. |
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2020-08-17 |
Luke Kenneth... | use longer memtest in litex sim |
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2020-08-17 |
Luke Kenneth... | adjust litex bios cmp test |
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2020-08-17 |
Luke Kenneth... | fix signed variants of cmp in alu |
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2020-08-17 |
Luke Kenneth... | add new cmp test for alu |
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2020-08-17 |
Luke Kenneth... | use shift module in mmu. to be moved to nmutil |
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2020-08-16 |
Cole Poirier | mmu.py fix formatting 80 char limit |
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2020-08-16 |
Luke Kenneth... | attempting to track down bug in litex bios memtest |
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2020-08-16 |
Luke Kenneth... | read delay on getting regfile data |
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2020-08-16 |
Luke Kenneth... | limit debug reporting in litex sim to range of pc |
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2020-08-16 |
Luke Kenneth... | cmp test from litex bios |
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2020-08-16 |
Luke Kenneth... | remove vhdl comments |
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2020-08-16 |
Luke Kenneth... | use simple one-line mask-generation |
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2020-08-16 |
Luke Kenneth... | fix LD/ST pimem issue with rising_edge detection |
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2020-08-16 |
Luke Kenneth... | missing vars, spelling corrections |
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2020-08-16 |
Luke Kenneth... | big reorg, shuffle code to functions, makes the FSM... |
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2020-08-16 |
Luke Kenneth... | spelling error, move perm_ok to local |
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2020-08-16 |
Luke Kenneth... | more comment removal |
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2020-08-16 |
Luke Kenneth... | more remove comments |
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2020-08-16 |
Luke Kenneth... | removing more comments, tidyup |
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2020-08-16 |
Luke Kenneth... | restore incorrect removal of zero-Cat at LHS (should... |
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2020-08-16 |
Luke Kenneth... | continue tidyup, comment removal/review. use byte_reve... |
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2020-08-16 |
Luke Kenneth... | fix batch of syntax errors found by running mmu.py |
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2020-08-16 |
Luke Kenneth... | begin tidyup, removing comments after line-by-line... |
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2020-08-15 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-15 |
Cole Poirier | mmu.py fix Cat() semantics fixes https://bugs.libre... |
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2020-08-15 |
Luke Kenneth... | thanks to daveshah, added simulation of dram |
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2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-15 |
Luke Kenneth... | rather big change to interaction between regfile and... |
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2020-08-15 |
Luke Kenneth... | clear compalu data latch always on issue |
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2020-08-15 |
Cesar Strauss | Demonstrates string traces |
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2020-08-15 |
Cesar Strauss | Demonstrates adding extra debug signals traces to the... |
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2020-08-15 |
Cesar Strauss | Demonstrates creating stylish GTKWave "save" files... |
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2020-08-14 |
Luke Kenneth... | remove latchregister, use sync to capture compunit... |
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2020-08-14 |
Luke Kenneth... | ha! "state" (pc, msr) not properly passed to core |
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2020-08-14 |
Luke Kenneth... | drop in insn_state synchronously in issuer, at same... |
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2020-08-14 |
Luke Kenneth... | submodule update |
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2020-08-14 |
Luke Kenneth... | hrfid unit test sets up HSRR0 and HSRR1 |
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2020-08-14 |
Luke Kenneth... | bad hack to get HSRR0/1 to be "same" as SRR0/1 |
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2020-08-14 |
Luke Kenneth... | bug in isa parser not recognising MSR as declared variable |
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2020-08-14 |
Luke Kenneth... | hack to get hrfid not to alter msr 51 |
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2020-08-14 |
Luke Kenneth... | stop trying to read swap files |
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2020-08-14 |
Luke Kenneth... | sync on alu results in compalu |
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2020-08-14 |
Luke Kenneth... | update submodule, add hrfid |
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2020-08-14 |
Luke Kenneth... | update submodule, add hrfid |
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2020-08-14 |
Luke Kenneth... | finally, fix decoder combinatorial loop |
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2020-08-14 |
Luke Kenneth... | fix test_compunit.py after moving decoder rdflags function |
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2020-08-14 |
Luke Kenneth... | add hrfid unit test |
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2020-08-14 |
Luke Kenneth... | sync up the core decode-execute state, |
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2020-08-14 |
Luke Kenneth... | move instruction decoder out of core |
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2020-08-14 |
Luke Kenneth... | move regspec / rdflag decoding functions out of PowerDe... |
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2020-08-14 |
Luke Kenneth... | sort out instruction stop/cancel when adding a new... |
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2020-08-14 |
Luke Kenneth... | put multi-ports back (for read) on int and fast regfiles |
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2020-08-14 |
Luke Kenneth... | reduce decoder pathways when exception occurs |
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2020-08-14 |
Luke Kenneth... | divide shiftrot pipeline into 2 (simple last) |
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2020-08-14 |
Luke Kenneth... | divide alu pipeline into 2 (simple last) |
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2020-08-14 |
Luke Kenneth... | divide logical pipe into 2 (simple phase last) |
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next |