soc.git
2021-11-19 Luke Kenneth... debug and cleanup
2021-11-19 Luke Kenneth... rename instruction_active to instr_active in core
2021-11-19 Luke Kenneth... read latch on regfile ports was fine, the combinatorial...
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth... latch copy of read register numbers, not in use due...
2021-11-19 Luke Kenneth... use read spec in connect_rdport rather than list of...
2021-11-19 Luke Kenneth... capture write regfile numbers into write latches in...
2021-11-19 Luke Kenneth... code tidyup / comments, and use defaultdict
2021-11-19 Luke Kenneth... create lists of latches in each FU, to record the read...
2021-11-19 Luke Kenneth... for some reason DMI CTRL returns status of 0x6 not 0x0
2021-11-19 Luke Kenneth... missing argument, domain="sync" in JTAG instance
2021-11-19 Luke Kenneth... return None if data returned is empty
2021-11-18 Luke Kenneth... remove combinatorial loop in core instruction conflict...
2021-11-18 Luke Kenneth... experimenting with overlapping instructions, bit of...
2021-11-18 Luke Kenneth... set up core processing FSM, which captures data if...
2021-11-18 Luke Kenneth... set up a temporary copy of CoreInput
2021-11-18 Luke Kenneth... experiment allowing overlap (activated with --allow...
2021-11-18 Luke Kenneth... remove unneeded import
2021-11-18 Tobias Platenmore work on test_loadstore1
2021-11-17 Jacob Lifshaystart adding bitmanip FU
2021-11-17 Tobias PlatenPortInterfaceBase: fix fast exception handling
2021-11-17 Tobias Platenwhitespace
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Tobias Platenfix mistake in test_pi2ls.py
2021-11-17 Luke Kenneth... reading of regfile bitvector added, which activates...
2021-11-17 Luke Kenneth... core hazard bitvector regfiles need to be readable
2021-11-17 Tobias Platenfixed busy waiting in pi_st
2021-11-17 Luke Kenneth... add option to test_issuer.py to allow for overlapping...
2021-11-17 Luke Kenneth... add ability to run hazard instruction for test purposes
2021-11-17 Luke Kenneth... detect the case in Core bitvector when the Function...
2021-11-17 Luke Kenneth... add probe of whether CompUnit ALU is done or not.
2021-11-17 Luke Kenneth... missing optional check on make_hazard_vecs
2021-11-17 Luke Kenneth... move core hazard set/clear to separate function, for...
2021-11-17 Luke Kenneth... whoops context-indentation by mistake (no harm done...
2021-11-17 Luke Kenneth... add a FetchOutput pipeline data structure
2021-11-16 Luke Kenneth... print out regfile unary status, bit of name-cleanup
2021-11-16 Luke Kenneth... use a virtual regfile port for the hazard bitvectors
2021-11-16 Tobias Platenpi_ld busy waiting fix
2021-11-16 Tobias Platenloadstore1 now reports exception reason
2021-11-16 Luke Kenneth... create set/get ports for bitvectors
2021-11-16 Luke Kenneth... capture write port (wrflag) in byregfiles_spec for...
2021-11-16 Luke Kenneth... rename regports for bitvectors so that
2021-11-16 Luke Kenneth... starting to get write-clear of hazard vectors operating
2021-11-16 Luke Kenneth... whoops, hazard vectors were depth 1 width N
2021-11-15 Tobias Platenreport dar on exception + test case
2021-11-15 Tobias Platenadd test_loadstore1.py
2021-11-13 Luke Kenneth... add quick instructions on how to run pinouts.py to...
2021-11-13 Luke Kenneth... update submodule to make ngi pointer router pinouts
2021-11-13 Luke Kenneth... add new get_pinspec_resources function which creates...
2021-11-13 Luke Kenneth... code-comment for get_pinspecs()
2021-11-13 Luke Kenneth... start adding hazard vector setting in core (unfinished)
2021-11-11 Luke Kenneth... debug prints
2021-11-11 Luke Kenneth... fix regfile port names for "fast" port access (regreduc...
2021-11-11 Luke Kenneth... TODO, implement is_dcbz
2021-11-11 Luke Kenneth... code-comments
2021-11-11 Luke Kenneth... split out core input/output into separate file core_data.py
2021-11-11 Luke Kenneth... enable hazard vecs in core
2021-11-11 Luke Kenneth... add exact same number - and name - bitvector ports...
2021-11-11 Luke Kenneth... code-morph regfile port specs to a dictionary format...
2021-11-11 Luke Kenneth... invert numbering on CR HDLState.get_crregs
2021-11-10 Luke Kenneth... update store data reg 10 to 0xfe in virtmode mmu test
2021-11-10 Luke Kenneth... remove read of MSR, it is done by passing through Power...
2021-11-10 Luke Kenneth... allow MSR to be set in StateRegs in test_core.py
2021-11-10 Luke Kenneth... add $Display of oper_r.msr in LDSTCompUnit
2021-11-10 Luke Kenneth... whitespace
2021-11-10 Luke Kenneth... morph regfiles to add hazard vector make_vecs function
2021-11-10 Luke Kenneth... add fetch of MSR in LD/ST pipe_data
2021-11-10 Tobias Platenadd debug output for msr_pr
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Tobias Platentest testcase for exception
2021-11-10 Luke Kenneth... make core busy_o part of the CoreOutput data structure
2021-11-10 Luke Kenneth... add a "fu_found" signal to core, which allows for an...
2021-11-09 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-09 Tobias Platentest_issuer_mmu.py: add case_5_allsprs
2021-11-09 Luke Kenneth... add core instruction-issue PriorityPickers
2021-11-09 Luke Kenneth... comments
2021-11-09 Luke Kenneth... core.py: create a dictionary of lists of Function Units...
2021-11-09 Luke Kenneth... create function core conect_satellite_decoders
2021-11-09 Luke Kenneth... add cancel in to alu_ok / alu_valid in LDSTCompUnit
2021-11-09 Luke Kenneth... rename LDSTCompUnit cancel to canceln (because it is...
2021-11-09 Luke Kenneth... whoops must remember to do rdmaskn on LDSTCompUnit...
2021-11-08 Luke Kenneth... remove unit test that is unfinished
2021-11-08 Luke Kenneth... shorter way of getting FU busy signals
2021-11-08 Luke Kenneth... MultiCompUnit fixed to not need rdmask to be sustained...
2021-11-08 Luke Kenneth... in MultiCompUnit, put rdmaskn into src latch rather...
2021-11-08 Tobias Platenmmu unit test working again
2021-11-08 Luke Kenneth... remove unused variable
2021-11-08 Luke Kenneth... code comments
2021-11-08 Luke Kenneth... comments
2021-11-08 Luke Kenneth... remove issue_i from core, use i_valid instead to decide...
2021-11-08 Luke Kenneth... move "exception happened" detection from TestIssuer...
2021-11-08 Luke Kenneth... use p.i_valid in core instead of explicit signal ivalid_i
2021-11-08 Luke Kenneth... use Pipeline API o_ready instead of explicit core busy_...
2021-11-08 Luke Kenneth... convert core.py to Pipeline API, deriving from ControlBase
2021-11-08 Luke Kenneth... remove unneeded imports
2021-11-08 Luke Kenneth... move simple core input and output data to in/out data...
2021-11-07 Luke Kenneth... make FSMDivCoreStage properly conform to Stage API
2021-11-07 Luke Kenneth... add hazard vectors to Regfiles
2021-11-07 Luke Kenneth... add quick test of regfiles to output rtlil
2021-11-07 Luke Kenneth... switch over to single-entry (num_rows=1) ReservationSta...
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