soc.git
2020-09-28 Luke Kenneth... had to over-ride the wishbone functions on C4M TAP
2020-09-27 Cole Poiriericache.py fix translation mistake
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-27 Luke Kenneth... add Makefile for creating ls180.il
2020-09-27 Luke Kenneth... rename sys_clk_i to clk_24_i
2020-09-27 Luke Kenneth... add clock selection mechanism
2020-09-26 Luke Kenneth... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-26 Luke Kenneth... do not use simdec2 in test_pipe_caller
2020-09-26 Luke Kenneth... fix annoying alu test_pipe_caller bug, missing asmcode
2020-09-26 Luke Kenneth... add alternative PowerDecode2 to branch test_pipe_caller
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-26 Luke Kenneth... try svf test of DMI MSR
2020-09-26 Luke Kenneth... make check of LDSTMode.update conditional in PowerDecoder2
2020-09-26 Luke Kenneth... add ls180io.py
2020-09-26 Luke Kenneth... add openocd script to fire off svf test
2020-09-26 Luke Kenneth... get openocd svf test running, replicating jtag test
2020-09-26 Luke Kenneth... put test into "server" mode for connecting with openocd
2020-09-26 Luke Kenneth... create client-server version of jtag debug unit test
2020-09-26 Luke Kenneth... create client-server version of jtag debug unit test
2020-09-26 Luke Kenneth... class-ify jtagremote
2020-09-26 Luke Kenneth... send/receive jtagremote protocol
2020-09-26 Luke Kenneth... basic client/server socket example
2020-09-26 Luke Kenneth... add openocd configs
2020-09-26 Luke Kenneth... reduce sdram pins to smaller address and only 1 cs_n
2020-09-26 Luke Kenneth... only enable pads connections for ls180 for now
2020-09-25 Cole Poiriericache.py fix several subtle bugs that were lines that...
2020-09-25 Cole Poirierwb_types.py add reset value of 0b11111111 for WBSelType...
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-24 Luke Kenneth... do not have to use uart_litex gpio_litex names
2020-09-24 Luke Kenneth... add comments
2020-09-24 Luke Kenneth... enable GPIO pads through C4M JTAG
2020-09-24 Luke Kenneth... c4m iopad integration working
2020-09-24 Cole Poiriericache.py add some missing lines from icache.vhdl,...
2020-09-24 Cole Poiriermem_types.py wb_types.py add name constructor to all...
2020-09-24 Cole Poiriericache.py fixed all errors that raised python exception...
2020-09-24 Cesar StraussFix whitespace, remove unused imports
2020-09-24 Luke Kenneth... brackets round imports looks cleaner?
2020-09-24 Luke Kenneth... add jtag c4m pins which gives us a way to connect IO...
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-23 Luke Kenneth... cs_n and cke in sdram need to match in length
2020-09-23 Luke Kenneth... change litex sdram pinouts to ASIC type
2020-09-23 Luke Kenneth... redo litex SDCard to send out data/cmd o/i/en pins
2020-09-23 Luke Kenneth... sort out GPIO with i/o/oe in ls180
2020-09-23 Luke Kenneth... add ls180 pinmap text file
2020-09-23 Luke Kenneth... attempt GPIO bi-directional
2020-09-23 Luke Kenneth... add I2C master to ls180
2020-09-22 Luke Kenneth... add 2 PWMs (quick, easy to do)
2020-09-22 Luke Kenneth... move dmi_sim to separate module
2020-09-22 Jacob Lifshayupdate submodule url
2020-09-22 Jacob LifshayRevert "disable pia in div tests"
2020-09-22 Luke Kenneth... add openocd.cfg experiment
2020-09-22 Luke Kenneth... create a JTAG platform and connect it up. jtagremote...
2020-09-22 Luke Kenneth... add jtagremote to litex sim, add new "variant" to core...
2020-09-22 Luke Kenneth... link litex ls180soc JTAG pads
2020-09-22 Luke Kenneth... add jtag wishbone and jtag ports to libresoc litex...
2020-09-22 Luke Kenneth... add jtag interface to issuer_verilog
2020-09-22 Luke Kenneth... add sys_rst to Clock Reset Generator
2020-09-22 Luke Kenneth... add JTAG IOpads and rename rst to sys_rst
2020-09-22 Luke Kenneth... add similar platforms to ls180.py
2020-09-22 Luke Kenneth... add JTAG bus module
2020-09-22 Luke Kenneth... split out dmi2jtag into own unit test
2020-09-22 Luke Kenneth... submodule update
2020-09-22 Cesar StraussPort soc.experiment.alu_fsm to the new way of invoking...
2020-09-22 Luke Kenneth... disable pia in div tests
2020-09-22 Luke Kenneth... add MMU (commented out)
2020-09-21 Luke Kenneth... add missing file
2020-09-21 Luke Kenneth... add quick wishbone jtag test
2020-09-21 Luke Kenneth... experiment set dmi msr read
2020-09-21 Luke Kenneth... add DMI JTAG test
2020-09-21 Luke Kenneth... add JTAG basic unit test
2020-09-21 Luke Kenneth... arg complete rewrite of JTAG2DMI, based it on staf...
2020-09-20 Cesar StraussAdd induction proof for the FSM Shifter
2020-09-20 Cesar StraussAdd bounded proof to FSM Shifter
2020-09-20 Cesar StraussLet the formal engine create some test cases for the...
2020-09-20 Luke Kenneth... resolve issues in async sim: must not drive async clock...
2020-09-20 Luke Kenneth... still experimenting with async FF sync
2020-09-20 Luke Kenneth... continuing async clock experimenting
2020-09-20 Luke Kenneth... add an async clock synchronizer experiment
2020-09-20 Luke Kenneth... first version code-morph on dmi2jtag
2020-09-19 Luke Kenneth... add pc_o not connected
2020-09-19 Luke Kenneth... set ROM to empty, set SRAM to tiny 0x200, get things...
2020-09-19 Cesar StraussRemove demonstration code
2020-09-19 Luke Kenneth... urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5
2020-09-19 Luke Kenneth... disable internal RAM set SRAM to much smaller
2020-09-19 Luke Kenneth... shrink size of SRAM to 8k, move things around
2020-09-19 Luke Kenneth... add (disabled) tri-state GPIO
2020-09-19 Luke Kenneth... remove the gpio peripheral which was previously hard...
2020-09-19 Luke Kenneth... add 3x EINTs to ls180soc
2020-09-18 Luke Kenneth... add SPI, sdcard, preliminary GPIO to ls180 pinouts
2020-09-18 Luke Kenneth... argh got fed up trying to shoe-horn into sim.py
2020-09-18 Luke Kenneth... can remove unneeded overrides of Prev/Next Control
2020-09-17 Jacob Lifshayadd divwe regression test case
2020-09-17 Jacob Lifshayre-enable test case -- no longer goes into an infinite...
2020-09-17 Jacob Lifshayfix bug #492
2020-09-17 Jacob Lifshayreplace sim._state.timeline.now with sim._engine.now
2020-09-17 Luke Kenneth... add versa ecp5 fpga litex build script
2020-09-16 Cole Poiriercomplete first translation pass of dmi_dtm_xilinx.vhdl...
2020-09-16 Luke Kenneth... make a start on LS180 platform
2020-09-16 Cole Poirierinitial commit of JTAGToDMI debug interface translated...
2020-09-16 Cole Poirieradd template file/starting point (copy of litex/boards...
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