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sifive-blocks.git
2017-08-18
Shreesha Srinath
Merge pull request #34 from ss2783/master
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2017-08-18
Shreesha Srinath
Renamed ShiftReg to ShiftRegister
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2017-08-18
Shreesha Srinath
Updates to go with the fpga-shells directory
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2017-08-10
Wesley W. Terpstra
uart: make it easy to simulate large text printouts...
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2017-08-04
Shreesha Srinath
Merge pull request #31 from ss2783/fix-mockaon
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2017-08-03
Shreesha Srinath
mockaon: Adds logic to detect external rtc toggles
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2017-08-02
Albert Ou
Merge pull request #30 from sifive/spi
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2017-08-02
Albert Ou
spi: Fix invalid D channel response when flash interfac...
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2017-08-02
Henry Cook
allow bundle content params to be specified via a def...
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2017-07-26
Wesley W. Terpstra
spi: remove removed sink arg
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2017-07-25
Yunsup Lee
Merge pull request #27 from sifive/typed_pad_ctrl
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2017-07-25
Yunsup Lee
mockaon: rename pads to pins
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2017-07-25
Megan Wachs
Ports: Rename the 'fromXYZPort' to 'fromPort' since...
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2017-07-25
Megan Wachs
Merge remote-tracking branch 'origin/master' into typed...
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2017-07-25
Yunsup Lee
uart: use PeripheryBusParams.frequency to calculate...
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2017-07-24
Megan Wachs
Merge remote-tracking branch 'origin/master' into typed...
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2017-07-23
Henry Cook
periphery: peripherals now in coreplex (#26)
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2017-07-20
Megan Wachs
gpio: Add missing file
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2017-07-20
Megan Wachs
Add missing cloneType methods to pin bundles
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2017-07-20
Megan Wachs
i2c: Remove pluralization on the bundle name, i2c not...
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2017-07-19
Megan Wachs
Remove pluralization on interface names. Require clocks...
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2017-07-19
Megan Wachs
Make it possible to adjust the type of pad controls...
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2017-07-07
Henry Cook
Refactor package hierarchy. (#25)
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2017-06-30
Wesley W. Terpstra
vc707 axi enhancements (#24)
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2017-06-29
Wesley W. Terpstra
mig: fix MemoryDevice to use 'reg' properly
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2017-06-29
Wesley W. Terpstra
spi: include mem region (#23)
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2017-06-29
Wesley W. Terpstra
diplomacy: add reg-names to devices (#22)
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2017-06-19
Megan Wachs
gpio: Make IOF optional (#21)
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2017-06-15
Henry Cook
make some base bundle classes easier to clone (#20)
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2017-06-15
Wesley W. Terpstra
spi: add dts ranges field for memory mapped spi (#19)
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2017-06-13
Henry Cook
Merge pull request #18 from sifive/lazy-raw-module-imp
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2017-06-13
Megan Wachs
More Peripheral-to-pins cleanups
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2017-06-13
Megan Wachs
UART: actually return the pins, not just the module...
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2017-06-13
Megan Wachs
GPIO/SPI/I2C: Add sync stages in place of dummy variabl...
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2017-06-13
Megan Wachs
GPIO/SPI/I2C: Add sync stages in place of dummy variabl...
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2017-06-12
Henry Cook
periphery: convert periphery bundle traits to work...
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2017-06-10
Megan Wachs
Merge pull request #17 from sifive/peripheral_options
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2017-06-09
Megan Wachs
peripheral_options: Actually compiles
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2017-06-08
Megan Wachs
SPIFlash: make it listable
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2017-06-08
Megan Wachs
GPIO: Make GPIO peripheral another listable one
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2017-06-02
Wesley W. Terpstra
vc707axi: track rocketchip API changes (#16)
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2017-05-14
Wesley W. Terpstra
uart: power-on with the right divider for the design...
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2017-05-13
Wesley W. Terpstra
Merge pull request #14 from sifive/async-pcie
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2017-05-13
Wesley W. Terpstra
vc707mig: use an external ibuf
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2017-05-13
Wesley W. Terpstra
xilinxvc707pciex1: push to a dedicated clock domain
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2017-05-11
Wesley W. Terpstra
xilinx mig: put a buffer infront of the controller...
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2017-05-08
Wesley W. Terpstra
xilinxvc707pciex1: better wrapper for AXI4-Lite control...
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2017-05-03
Henry Cook
Merge pull request #10 from sifive/axi-mmio
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2017-05-02
Yunsup Lee
Merge pull request #11 from sifive/spi
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2017-05-02
Albert Ou
spi: Fix off-by-one error in calculating cycles per...
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2017-05-02
Albert Ou
spi: Fix io.port.dq(3) output enable
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2017-04-26
Wesley W. Terpstra
axi4: switch to new pipelined converters
axi-mmio
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2017-04-25
Henry Styles
Merge pull request #9 from sifive/vc707_mig_analog_inout
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2017-04-25
Henry Styles
Use _chisel3 analog for MIG inout
vc707_mig_analog_inout
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2017-04-25
solomatnikov
Added stall for read after write (#8)
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2017-04-10
Megan Wachs
Merge pull request #7 from sifive/ndreset
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2017-04-07
Megan Wachs
MockAON: Accept the non-debug interrupt as an input...
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2017-03-31
Megan Wachs
Merge pull request #6 from sifive/debug_v013
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2017-03-31
Megan Wachs
spi: correct polarity of FIRRTL combo loop detection...
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2017-03-31
Megan Wachs
Merge remote-tracking branch 'origin/fix-false-comb...
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2017-03-31
Jack Koenig
"Fix" false combinational loop through SPIArbiter
fix-false-comb-loop
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2017-03-28
Megan Wachs
Merge remote-tracking branch 'origin/master' into debug...
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2017-03-26
Yunsup Lee
rename l2FrontendBus as fsb
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2017-03-25
Yunsup Lee
rename l2FrontendBus as fsb
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2017-03-25
Megan Wachs
JTAG: make TRSTn optional for all helpers as well to...
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2017-03-23
Megan Wachs
Merge remote-tracking branch 'origin/master' into debug...
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2017-03-22
Yunsup Lee
update TLRegisterNode to take Seq of AddressSet
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2017-03-22
Megan Wachs
TLSPI: address parameter must now be a sequence.
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2017-03-14
Megan Wachs
Adjust JTAG for rocket-chip changes
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2017-03-10
Megan Wachs
Merge remote-tracking branch 'origin/master' into debug...
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2017-03-03
Wesley W. Terpstra
xilinx pcie: add the high PCIe address bits (physical...
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2017-03-03
Wesley W. Terpstra
Merge pull request #4 from sifive/periphery-keys
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2017-03-03
Wesley W. Terpstra
devices: include DTS meta-data
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2017-03-03
Wesley W. Terpstra
devices: create periphery keys for all devices
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2017-03-02
Megan Wachs
jtag: The jtag interfaces have moved to a different...
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2017-02-17
Megan Wachs
Merge pull request #2 from sifive/homogenous_bag_periph...
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2017-02-17
Megan Wachs
Use HomogenousBag to handle lists of peripherals
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2017-02-10
solomatnikov
Merge pull request #1 from sifive/i2c
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2017-02-10
Alex Solomatnikov
Merge remote-tracking branch 'origin/master' into i2c
i2c
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2017-02-09
Alex Solomatnikov
Flipped polarity of output enables to match Guava pins...
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2017-02-09
Alex Solomatnikov
Made regs 32-bit word aligned to match the rest of...
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2017-02-08
Alex Solomatnikov
Added note: WISHBONE interface replaced by Tilelink2
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2017-02-07
Alex Solomatnikov
Added license
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2017-02-06
Alex Solomatnikov
Renamed i2cDevices to i2c
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2017-02-04
Wesley W. Terpstra
xilinx mig: track changes in rocket-chip
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2017-02-04
Alex Solomatnikov
Addressing comments: bool style, comments, removed...
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2017-02-04
Alex Solomatnikov
Bug fixes: passing OC WB test
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2017-02-01
Wesley W. Terpstra
sifive-blocks: trust diplomacy to get names right
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2017-02-01
Alex Solomatnikov
Completed Chisel RTL (not tested yet)
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2017-01-31
Wesley W. Terpstra
spi: work around ucb-bar/chisel3#472
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2017-01-30
Wesley W. Terpstra
xilinx ip: adjust to new diplomacy API
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2017-01-24
Alex Solomatnikov
Initial (compilable) version of I2C (no actual logic...
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2017-01-21
Wesley W. Terpstra
xilinx pcie: put buffers before the outputs to the...
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2017-01-20
Wesley W. Terpstra
mig: track change to Blind port API in rocket
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2016-12-07
Wesley W. Terpstra
LazyModule: provide Parameters
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2016-12-07
Wesley W. Terpstra
xilinx pcie: bytes, not bits
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2016-12-03
Wesley W. Terpstra
RegMapFIFO: amoor.w can do thread-safe TX
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2016-11-30
Richard Xia
Add /target to .gitignore.
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2016-11-29
SiFive
Initial commit.
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