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riscv-tests.git
2018-09-13
Tim Newsome
Assert if HiFive1 program is too large.
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2018-09-13
Tim Newsome
Put debug test stack in data instead of text
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2018-09-08
Andrew Waterman
Merge branch 'tommythorn-master'
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2018-09-08
Tommy Thorn
RV64 s{ll,ra,rl}w tests with non-canonical values
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2018-09-07
Andrew Waterman
Revert "breakpoint.S: Don't assume trigger is hardwired...
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2018-09-06
Tommy Thorn
breakpoint.S: Don't assume trigger is hardwired to...
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2018-09-03
Tim Newsome
Merge pull request #156 from riscv/PrivChange
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2018-08-31
Tim Newsome
Fix CustomRegisterTest.
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2018-08-29
Tim Newsome
Add test case for `riscv expose_custom`.
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2018-08-28
Tim Newsome
Reset address translation/perms before PrivChange
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2018-08-28
Tim Newsome
Neuter TriggerStoreAddressInstant
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2018-08-27
Tim Newsome
Make pylint happy.
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2018-08-25
Andrew Waterman
Temporarily disabling PrivChange test
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2018-08-24
Tim Newsome
Make pylint happy with change d1d2d953b5016b465.
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2018-08-24
Tim Newsome
Get all of the log into the final log file
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2018-08-23
Tim Newsome
Merge pull request #153 from dmitryryzhov/rtos-switch...
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2018-08-22
Tim Newsome
Merge branch 'master' of https://github.com/riscv/riscv...
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2018-08-22
Tim Newsome
Disable MulticoreRunHaltStepiTest
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2018-08-22
Dmitry Ryzhov
Add debug test, which checks that openocd correctly...
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2018-08-21
Srivatsa Yogendra
Changing the register mstatus is read into (#152)
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2018-08-21
Andrew Waterman
Revert "Fix to solve the failing tests shamt, csr and...
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2018-08-18
Srivatsa Yogendra
Fix to solve the failing tests shamt, csr and scall...
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2018-08-17
Srivatsa Yogendra
making mtvec_handler global (#150)
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2018-08-13
Tim Newsome
Add jump/hbreak test.
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2018-07-09
Andrew Waterman
Check that SC yields the load reservation
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2018-07-03
Tim Newsome
rwatch/watch on explicit address
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2018-06-18
Tim Newsome
Add reproduce line to the end of debug test logs
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2018-05-21
Tim Newsome
Merge pull request #141 from riscv/mrhstest
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2018-05-19
Tim Newsome
Fix MulticoreRunHaltStepiTest
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2018-05-15
Megan Wachs
Merge pull request #139 from riscv/debug-tests-more...
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2018-05-14
Megan Wachs
Merge remote-tracking branch 'origin/downloadtest'...
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2018-05-14
Tim Newsome
Make DownloadTest properly park other harts.
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2018-05-14
Megan Wachs
debug: remove some unintentionally added newlines
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2018-05-14
Megan Wachs
debug: Fixing the non-RTOS behavior for DownloadTest
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2018-05-11
Megan Wachs
debug: mark more tests as single-hart tests
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2018-05-11
Megan Wachs
debug: output some more useful info into the post-morte...
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2018-05-01
Christopher...
[rv64ua/lrsc] Initialize memory read out. (#135)
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2018-04-30
Tim Newsome
Fix formatting to make pylint happy.
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2018-04-29
Megan Wachs
Merge pull request #132 from riscv/debug-clear-satp
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2018-04-27
Megan Wachs
debug: need to clear satp before changing priv
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2018-04-27
Megan Wachs
Merge pull request #125 from riscv/debug-delete-sim
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2018-04-27
Megan Wachs
Merge pull request #130 from riscv/trap_entry_align-1
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2018-04-27
Megan Wachs
debug: add missing align directive on trap_entry
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2018-04-24
Tim Newsome
Fix race when making logs directory
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2018-04-19
Megan Wachs
Delete E300Sim.py
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2018-04-16
Tim Newsome
Merge pull request #123 from riscv/gdb_timeout
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2018-04-09
Tim Newsome
Compute gdb command timeout based on ops estimate
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2018-04-09
Andrei Tatarnikov
Fix #120: Instructions 'sll' are replaced with 'slli...
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2018-04-02
Tim Newsome
Use `gdb_report_register_access_error enable`
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2018-03-27
Tim Newsome
Test debug authentication.
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2018-03-23
Tim Newsome
Print log filename at the end of the log.
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2018-03-21
Andrew Waterman
Make misa.C test conform to Hauser proposal
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2018-03-21
Palmer Dabbelt
Merge pull request #119 from rishikhan/master
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2018-03-19
rishi
Update Makefile to allow for RISCV_PREFIX to be set...
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2018-03-01
Tim Newsome
Test debugging with/without a program buffer
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2018-03-01
Tim Newsome
Ensure an error when reading a non-existent CSR.
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2018-02-27
Andrew Waterman
Add test for clearing misa.C while PC is misaligned...
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2018-02-09
Tim Newsome
Test resuming from a trigger.
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2018-02-07
Tim Newsome
Link scripts shouldn't be executable.
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2018-01-08
Tim Newsome
Deal with gdb reporting pmpcfg0 not existing.
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2018-01-05
Tim Newsome
Add test for multicore failure
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2018-01-03
Andrew Waterman
Test access exception behavior for illegal addresses...
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2017-12-27
Tim Newsome
Test FPRs that aren't XLEN in size.
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2017-12-22
Tim Newsome
Add all-tests target.
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2017-12-21
Megan Wachs
Merge pull request #110 from riscv/bump_env
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2017-12-21
Megan Wachs
tests: bump env to pick up new names for CSRs
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2017-12-20
Tim Newsome
Remove `set arch riscv:rv%d`
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2017-12-20
Tim Newsome
Verify that F18 does not exist on FPU-less targets
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2017-12-12
Tim Newsome
Display env variables used when invoking OpenOCD
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2017-12-01
Tim Newsome
Ensure there are no unnamed registers.
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2017-11-30
Tim Newsome
Merge pull request #109 from riscv/vcssim
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2017-11-30
Tim Newsome
Clean up VcsSim init()
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2017-11-27
Andrew Waterman
Rename sbadaddr to satp
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2017-11-27
Torbjørn
Rv32ud tests (#108)
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2017-11-22
Christopher...
Check sepc for rv64si/scall test. (#107)
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2017-11-20
Andrew Waterman
Check mtval in rv64mi-p-illegal (#104)
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2017-11-20
Tim Newsome
Ensure log file is fully written before reading it
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2017-11-20
Tim Newsome
Make pylint happy.
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2017-11-17
Megan Wachs
Merge pull request #102 from riscv/xlen_fix
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2017-11-17
Megan Wachs
debug: Fix the XLEN command line check
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2017-11-17
Megan Wachs
Debug: Use the --32 and --64 command line arguments...
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2017-11-16
Tim Newsome
Disable PMP for PrivRw test.
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2017-11-16
Tim Newsome
Clarify PrivTest detail.
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2017-11-12
Andrew Waterman
Make sure that code is 4-byte aligned before disabling...
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2017-11-10
Andrew Waterman
Make rv64mi-p-ecall work when U-mode is not present
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2017-11-10
Andrew Waterman
Use mstatus.MPP to check existence of U-mode
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2017-11-02
Tim Newsome
Add --print-log-names to print temp log names ASAP
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2017-11-02
Tim Newsome
Ensure gdb connection failures end up in main log.
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2017-11-02
Megan Wachs
debug: Need to apply remotetimeout before connecting...
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2017-11-01
Christopher...
SBREAK test now checks EPC value. (#92)
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2017-11-01
Tim Newsome
Make pylint 1.6.5 happy.
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2017-11-01
Tim Newsome
Test register aliases in the simple register tests
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2017-11-01
Tim Newsome
Fix MulticoreRegTest.
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2017-10-31
Palmer Dabbelt
Merge pull request #90 from richardxia/comment-out...
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2017-10-31
Richard Xia
Temporarily comment out MulticoreRegTest due to flakiness.
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2017-10-30
Richard Xia
Remove cache miss test from last AMO test. (#88)
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2017-10-30
Richard Xia
Declare trap handlers as global symbols. (#87)
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2017-10-27
Andrew Waterman
Verify that mtval/stval is written correctly on misalig...
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2017-10-27
Richard Xia
Fix rv64mi-csr for the case where U-mode is not availab...
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2017-10-24
Tim Newsome
Increase dual-core RV64 timeouts.
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