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soclayout.git
2021-04-28 Luke Kenneth... create function which pre-creates the blackbox cells commit | commitdiff | tree
2021-04-28 Luke Kenneth... name everything back to spblock_512w64b8w now that... commit | commitdiff | tree
2021-04-28 Luke Kenneth... rename spblock modules to just straight spblock_512w64b... commit | commitdiff | tree
2021-04-28 Luke Kenneth... also add createSRAMblocks to freepdk_c4m45 commit | commitdiff | tree
2021-04-28 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922... commit | commitdiff | tree
2021-04-28 Jean-Paul ChaputManagement of SRAMs block at Coriolis devel. commit | commitdiff | tree
2021-04-28 Luke Kenneth... add vbe spblock models to non_generated and build scripts commit | commitdiff | tree
2021-04-28 Luke Kenneth... shrinking regfile sizes some more commit | commitdiff | tree
2021-04-27 Luke Kenneth... add blackbox attribute to spblock512*.v commit | commitdiff | tree
2021-04-27 Luke Kenneth... also add blackboxes spblock512* etc. commit | commitdiff | tree
2021-04-27 Luke Kenneth... add copying over of spblock*.v and pll.v to build scripts commit | commitdiff | tree
2021-04-25 Luke Kenneth... submodule update commit | commitdiff | tree
2021-04-25 Jean-Paul ChaputCorrect setup for experiment9/freepdk_c4m45, restrict... commit | commitdiff | tree
2021-04-24 Luke Kenneth... update submodule commit | commitdiff | tree
2021-04-24 Luke Kenneth... cleanup mksyms.sh to include FreePDK_C4M45 commit | commitdiff | tree
2021-04-24 Luke Kenneth... add export of PDKMASTER_TOP to experiments9/freepdk_c4m45 commit | commitdiff | tree
2021-04-24 Luke Kenneth... correct relative link to FreePDK45_c4m45, use submodule commit | commitdiff | tree
2021-04-24 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922... commit | commitdiff | tree
2021-04-24 Jean-Paul ChaputForgot to update experiments9 doDesign file for FreePDK 45. commit | commitdiff | tree
2021-04-24 Jean-Paul ChaputKeep in synch with the latest Coriolis. SRAM models... commit | commitdiff | tree
2021-04-24 Jean-Paul ChaputCorrect settings for experiment10_verilog & FreePDK45. commit | commitdiff | tree
2021-04-22 Luke Kenneth... make placement of SRAMs optional, and PLL as well,... commit | commitdiff | tree
2021-04-20 Luke Kenneth... manually comment out pll and sdcard pins commit | commitdiff | tree
2021-04-19 Staf Verhaegenexperiments10_verilog/freepdk_c4m45: Add link for add.py. commit | commitdiff | tree
2021-04-19 Staf VerhaegenTop layer -> metal6 commit | commitdiff | tree
2021-04-19 Staf Verhaegenexperiments9/freepdk_c4m45: Reduce core size. commit | commitdiff | tree
2021-04-19 Luke Kenneth... add SPBlock512 instance generator commit | commitdiff | tree
2021-04-19 Luke Kenneth... code-comments commit | commitdiff | tree
2021-04-19 Luke Kenneth... add two SRAMs, document how to do more commit | commitdiff | tree
2021-04-18 Luke Kenneth... argh, found the blackbox problem: yosys is "doing the... commit | commitdiff | tree
2021-04-18 Luke Kenneth... try renaming spblock without the underscore commit | commitdiff | tree
2021-04-18 Luke Kenneth... try changing layout of blackbox spblock_512w64b8w commit | commitdiff | tree
2021-04-18 Luke Kenneth... experimenting with blackboxes commit | commitdiff | tree
2021-04-18 Luke Kenneth... rename spblock_512w64b8w, and vco_test_ana for pll commit | commitdiff | tree
2021-04-18 Luke Kenneth... rename blackboxes to lowercase, spblock_512w64b8w, pll commit | commitdiff | tree
2021-04-18 Luke Kenneth... update ls180 sram4k commit | commitdiff | tree
2021-04-18 Luke Kenneth... add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst... commit | commitdiff | tree
2021-04-18 Luke Kenneth... must use VST_FLAGS uniquify uppercase commit | commitdiff | tree
2021-04-18 Luke Kenneth... sort out adding SPBlock_512 SRAM verilog to ls180 commit | commitdiff | tree
2021-04-18 Luke Kenneth... update tsmc_018 4k build script commit | commitdiff | tree
2021-04-18 Luke Kenneth... use correct arguments to litex build to create 4k srams... commit | commitdiff | tree
2021-04-18 Luke Kenneth... rename ls180sram4k to ls180 commit | commitdiff | tree
2021-04-18 Luke Kenneth... add full core variant including 4k sram of ls180 commit | commitdiff | tree
2021-04-18 Luke Kenneth... update libresoc.v, c4m-jtag fsm was renamed commit | commitdiff | tree
2021-04-18 Luke Kenneth... update libresoc.v, c4m-jtag fsm was renamed commit | commitdiff | tree
2021-04-14 Luke Kenneth... add an SRAM and wishbone to add test (makes it bigger) commit | commitdiff | tree
2021-04-14 Luke Kenneth... connect up boundary scan to inputs/outputs commit | commitdiff | tree
2021-04-13 Luke Kenneth... submodule update commit | commitdiff | tree
2021-04-13 Luke Kenneth... use METAL10 for topRoutingLayer commit | commitdiff | tree
2021-04-13 Luke Kenneth... whoops forgot settings.py commit | commitdiff | tree
2021-04-12 Luke Kenneth... submodule update commit | commitdiff | tree
2021-04-12 Luke Kenneth... set routingGauge manually commit | commitdiff | tree
2021-04-12 Luke Kenneth... enable HFNS in adder commit | commitdiff | tree
2021-04-12 Luke Kenneth... include (but do not use) FreePDK45 in experiments10 commit | commitdiff | tree
2021-04-12 Luke Kenneth... different FreePDK45 experiments10 chip size commit | commitdiff | tree
2021-04-12 Luke Kenneth... experimentation to get experiment10_verilog work with... commit | commitdiff | tree
2021-04-12 Luke Kenneth... add FreePDK45 experiments10_verilog doDesign.py commit | commitdiff | tree
2021-04-12 Luke Kenneth... add FreePDK45 variant of experiments10_verilog commit | commitdiff | tree
2021-04-12 Luke Kenneth... update PLL signal output names commit | commitdiff | tree
2021-04-12 Staf VerhaegendoDesign.py: Disable SRAM placement commit | commitdiff | tree
2021-04-12 Staf VerhaegenReduce core size. commit | commitdiff | tree
2021-04-12 Luke Kenneth... rename sys_clk in adder test experiments10_verilog... commit | commitdiff | tree
2021-04-12 Luke Kenneth... rename JTAG port in adder test experiments10_verilog... commit | commitdiff | tree
2021-04-12 Luke Kenneth... back to "working" verilog add commit | commitdiff | tree
2021-04-12 Luke Kenneth... another attempt to get 100% completed route commit | commitdiff | tree
2021-04-12 Staf VerhaegenRight branch of c4m-pdk-freedpk45. commit | commitdiff | tree
2021-04-11 Luke Kenneth... good grief, increasing ls180 core size to 70,000, 100... commit | commitdiff | tree
2021-04-11 Luke Kenneth... increase core size to see if global routing can be... commit | commitdiff | tree
2021-04-11 Luke Kenneth... whitespace cleanup commit | commitdiff | tree
2021-04-11 Luke Kenneth... use auto-generated pinmux ioPadsSpecs commit | commitdiff | tree
2021-04-11 Luke Kenneth... submodule conflict (update again) commit | commitdiff | tree
2021-04-11 Luke Kenneth... use verilog version of ls180 in FreePDK_c4m45 commit | commitdiff | tree
2021-04-11 Staf VerhaegenUpdate c4m-pdk-freepdk45 submodule. commit | commitdiff | tree
2021-04-11 Luke Kenneth... crank up the numbers (again) commit | commitdiff | tree
2021-04-11 Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45. commit | commitdiff | tree
2021-04-11 Staf Verhaegenexperiments9: Ignore pinmux generated files. commit | commitdiff | tree
2021-04-11 Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit commit | commitdiff | tree
2021-04-11 Staf VerhaegenSubmodule for C4M FreePDK45 PDK release files. commit | commitdiff | tree
2021-04-11 Luke Kenneth... crank up the numbers to see if routing completion can... commit | commitdiff | tree
2021-04-11 Luke Kenneth... increase katana tracks reserved commit | commitdiff | tree
2021-04-10 Luke Kenneth... use verilog for ls180 instead of ilang commit | commitdiff | tree
2021-04-10 Luke Kenneth... make VST names unique, for GHDL to cope commit | commitdiff | tree
2021-04-09 Luke Kenneth... sigh, broken experiment10_verilog commit | commitdiff | tree
2021-04-09 Luke Kenneth... whitespace commit | commitdiff | tree
2021-04-09 Luke Kenneth... whitespace cleanup commit | commitdiff | tree
2021-04-09 Luke Kenneth... pad name starts with p_ commit | commitdiff | tree
2021-04-09 Luke Kenneth... rename design of experiments10 to match ls180 chip... commit | commitdiff | tree
2021-04-02 Luke Kenneth... experiment with nmigen verilog generation commit | commitdiff | tree
2021-04-01 Luke Kenneth... update / refresh full core DFF commit | commitdiff | tree
2021-04-01 Luke Kenneth... update / refresh full core DFF commit | commitdiff | tree
2021-04-01 Luke Kenneth... run doChipFloorplan in experiments10 commit | commitdiff | tree
2021-04-01 Luke Kenneth... increase experiment10 JTAG tap width to 4 commit | commitdiff | tree
2021-04-01 Luke Kenneth... update submodule commit | commitdiff | tree
2021-03-30 Luke Kenneth... update 4k SRAM ls180.il commit | commitdiff | tree
2021-03-30 Luke Kenneth... add yosys version number commit | commitdiff | tree
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922... commit | commitdiff | tree
2021-03-29 Jean-Paul ChaputAdd a placeholder for the PLL in the doDesign.py for... commit | commitdiff | tree
2021-03-29 Luke Kenneth... Revert "enable high fanout in ls180 experiment9 doDesig... commit | commitdiff | tree
2021-03-29 Luke Kenneth... enable high fanout in ls180 experiment9 doDesign.py commit | commitdiff | tree
2021-03-29 Luke Kenneth... aaagh found bug in litex setup, 64 bit WB bus was truncated commit | commitdiff | tree
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