| 2020-07-01 | 
Luke Kenneth...  | whoops swapped trap test instructions accidentally | 
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| 2020-07-01 | 
Luke Kenneth...  | print out msr for debug | 
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| 2020-07-01 | 
Luke Kenneth...  | attempting to add SPRs to rfid test | 
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| 2020-07-01 | 
Luke Kenneth...  | add OP_SC | 
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| 2020-07-01 | 
Luke Kenneth...  | trap test check results | 
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| 2020-07-01 | 
Luke Kenneth...  | add name "test_issuer" to ilang conversion | 
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| 2020-07-01 | 
Luke Kenneth...  | add in trap compunit | 
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| 2020-07-01 | 
Luke Kenneth...  | add rfid and td/tw trap test | 
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| 2020-07-01 | 
Luke Kenneth...  | continue debugging trap pipeline | 
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| 2020-07-01 | 
Luke Kenneth...  | debugging trap pipeline | 
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| 2020-07-01 | 
Luke Kenneth...  | start running trap unit test, fixing errors | 
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| 2020-06-30 | 
Luke Kenneth...  | add lte ltu for use by twi and other trap functions | 
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| 2020-06-30 | 
Luke Kenneth...  | add in pseudocode keyword into mdwn isa files | 
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| 2020-06-30 | 
Luke Kenneth...  | code-morph on div pipeline | 
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| 2020-06-29 | 
Luke Kenneth...  | add README for fu directory | 
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| 2020-06-29 | 
Luke Kenneth...  | use correct ALUHelpers in div test | 
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| 2020-06-29 | 
Luke Kenneth...  | sort out syntax errors in div | 
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| 2020-06-29 | 
Luke Kenneth...  | first unit test for div | 
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| 2020-06-29 | 
Luke Kenneth...  | update submodule to fix div bug | 
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| 2020-06-29 | 
Luke Kenneth...  | add ignore for parsetab.py | 
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| 2020-06-29 | 
Luke Kenneth...  | add autogenerated do not commit comment | 
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| 2020-06-29 | 
Luke Kenneth...  | update submodule to div overflow | 
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| 2020-06-29 | 
Luke Kenneth...  | separate out divide by zero cases | 
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| 2020-06-29 | 
Luke Kenneth...  | update OV and OV32 ISACaller flags if overflow occurs | 
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| 2020-06-29 | 
Luke Kenneth...  | attempting to add overflow setting in ISACaller | 
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| 2020-06-29 | 
Luke Kenneth...  | whoops, hex parser digits are in multiples of 4 bits | 
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| 2020-06-29 | 
Luke Kenneth...  | fetch instructions from bare wishbone fetch unit | 
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| 2020-06-28 | 
Cesar Strauss | Start with a simpler test case | 
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| 2020-06-28 | 
Cesar Strauss | Let p.ready_o be active while the test ALU is idle | 
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| 2020-06-28 | 
Luke Kenneth...  | add cached fetch unit pass-through args | 
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| 2020-06-28 | 
Luke Kenneth...  | need args to WishboneArbiter, match data width size | 
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| 2020-06-28 | 
Cesar Strauss | Add missing ports to the test ALU | 
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| 2020-06-28 | 
Luke Kenneth...  | read from instruction memory using FetchUnitInterface | 
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| 2020-06-28 | 
Luke Kenneth...  | add Config Fetch interface and quick unit test | 
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| 2020-06-28 | 
Luke Kenneth...  | add test instruction memory | 
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| 2020-06-28 | 
Luke Kenneth...  | add readonly option to TestMemory | 
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| 2020-06-28 | 
Luke Kenneth...  | expand instruction bus width to 64 bit, start on a...  | 
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| 2020-06-28 | 
Luke Kenneth...  | parameterise minerva i-cache | 
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| 2020-06-28 | 
Luke Kenneth...  | got Pi2LSUI FSM working | 
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| 2020-06-28 | 
Luke Kenneth...  | sram address do not cut by LSBs | 
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| 2020-06-28 | 
Luke Kenneth...  | new Pi2LSUI working, using PortInterfaceBase | 
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| 2020-06-28 | 
Luke Kenneth...  | start new version of Pi2LSUI based on PortInterfaceBase | 
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| 2020-06-28 | 
Luke Kenneth...  | pass addr/mask through to PortInterfaceBase rd/wr addr | 
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| 2020-06-28 | 
Luke Kenneth...  | cleanup (remove unneeded imports) | 
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| 2020-06-28 | 
Luke Kenneth...  | more code-shuffle for TestMemoryPortInterface | 
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| 2020-06-28 | 
Luke Kenneth...  | more code-shuffle for TestMemoryPortInterface | 
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| 2020-06-28 | 
Luke Kenneth...  | minor cleanup, put get/set rdport/wrport into function | 
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| 2020-06-28 | 
Luke Kenneth...  | merge LDSTPort into TestMemoryPortInterface | 
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| 2020-06-28 | 
Luke Kenneth...  | use PortInterface connect_port | 
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| 2020-06-28 | 
Luke Kenneth...  | use PortInterface connect_port | 
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| 2020-06-28 | 
Luke Kenneth...  | attempt to get Pi2LSUI FSM working | 
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| 2020-06-27 | 
Luke Kenneth...  | only activate ld_in_progress if addr is ok | 
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| 2020-06-27 | 
Luke Kenneth...  | make Memory accessible via TestSRAMBareLoadStoreUnit | 
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| 2020-06-27 | 
Luke Kenneth...  | increase (double) address width in TstL0CacheBuffer | 
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| 2020-06-27 | 
Luke Kenneth...  | increase (double) address width in TstL0CacheBuffer | 
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| 2020-06-27 | 
Luke Kenneth...  | unit test in l0_cache to connect to testpi and test_bare_wb | 
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| 2020-06-27 | 
Luke Kenneth...  | make PortInterface modules consistent with same API | 
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| 2020-06-27 | 
Luke Kenneth...  | use ConfigMemoryPortInterface in TstL0CacheBuffer | 
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| 2020-06-27 | 
Luke Kenneth...  | fix TestMemLoadStoreUnit, it required a FSM to monitor...  | 
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| 2020-06-27 | 
Luke Kenneth...  | add wishbone Pi2LSUI test | 
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| 2020-06-27 | 
Luke Kenneth...  | reconfigureable PortInterface testing now possible | 
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| 2020-06-26 | 
Luke Kenneth...  | name issue in Pi2LSUI | 
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| 2020-06-26 | 
Luke Kenneth...  | whitespace and imports | 
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| 2020-06-26 | 
Luke Kenneth...  | whitespace | 
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| 2020-06-26 | 
Luke Kenneth...  | slight reorg on test_pi2ls.py | 
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| 2020-06-26 | 
Luke Kenneth...  | correct address in pi2ls | 
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| 2020-06-26 | 
Luke Kenneth...  | oops forgot to initialise base class of TestMemLoadStor...  | 
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| 2020-06-26 | 
Luke Kenneth...  | add in LenExpand shift/mask | 
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| 2020-06-26 | 
Luke Kenneth...  | add quick test showing Pi2LSUI not quite reading/writing to | 
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| 2020-06-26 | 
Luke Kenneth...  | remove extraneous yields | 
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| 2020-06-26 | 
Michael Nolan | Modify pi2ls so it passes the portinterface unit tests | 
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| 2020-06-26 | 
Luke Kenneth...  | set address ok and fix unit test to check it properly | 
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| 2020-06-26 | 
Luke Kenneth...  | add pi.busy_o connection, increase to 64 bit | 
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| 2020-06-26 | 
Luke Kenneth...  | unit test broken is ok :) | 
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| 2020-06-26 | 
Luke Kenneth...  | set pi.ld.ok to 1 if pi.is_ld_i is set | 
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| 2020-06-26 | 
Michael Nolan | Move tests for pimem to new file, add ability to test...  | 
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| 2020-06-26 | 
Luke Kenneth...  | load/store unit test needed to wait for busy_o | 
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| 2020-06-26 | 
Luke Kenneth...  | whitespace | 
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| 2020-06-26 | 
Luke Kenneth...  | clean up output from BareLoadStoreUnit | 
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| 2020-06-26 | 
Luke Kenneth...  | halve the test memory size again | 
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| 2020-06-26 | 
Luke Kenneth...  | shrink test memory size down to only 64 words | 
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| 2020-06-26 | 
Luke Kenneth...  | investigating why write-enable not getting passed through | 
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| 2020-06-26 | 
Luke Kenneth...  | whoops forgot to call parent elaborate | 
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| 2020-06-26 | 
Luke Kenneth...  | add test of SRAM through wishbone bus | 
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| 2020-06-26 | 
Luke Kenneth...  | code-morph which redirects lsmem unit test through...  | 
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| 2020-06-26 | 
Luke Kenneth...  | add a test SRAM that lives behind a minerva LoadStoreUn...  | 
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| 2020-06-26 | 
Luke Kenneth...  | dynamically specify wishbone layout (no longer hardcode...  | 
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| 2020-06-26 | 
Luke Kenneth...  | add reconfigureable Load/Store class | 
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| 2020-06-26 | 
Luke Kenneth...  | extra parameterification of minerva LoadStoreUnits | 
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| 2020-06-25 | 
Luke Kenneth...  | allow Pi2LSUI to accept incoming PortInterface and...  | 
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| 2020-06-25 | 
Luke Kenneth...  | add extra parameter, mask_wid, to TestMemLoadStoreUnit | 
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| 2020-06-25 | 
Luke Kenneth...  | start connecting up Pi2LSUI | 
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| 2020-06-25 | 
Luke Kenneth...  | add LenExpand module, tidyup on docstring | 
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| 2020-06-25 | 
Luke Kenneth...  | add beginnings of Pi2LSUI | 
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| 2020-06-25 | 
Luke Kenneth...  | add nmigen-soc to dependencies | 
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| 2020-06-25 | 
Luke Kenneth...  | add attempt at mapping between PortInterface and LoadSt...  | 
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| 2020-06-25 | 
Luke Kenneth...  | rename LoadStoreInterface signals to include _i and...  | 
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| 2020-06-25 | 
Luke Kenneth...  | whitespace | 
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| 2020-06-24 | 
Michael Nolan | Revert "modify PortInterface so subfields include the...  | 
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| 2020-06-24 | 
Michael Nolan | Update comments for LoadStoreUnitInterface | 
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| next |