test of fp16 elwidth
[riscv-tests.git] / isa /
2018-10-31 Luke Kenneth Casso... test of fp16 elwidth
2018-10-30 Luke Kenneth Casso... add fp add elwidth single-precision test
2018-10-30 Luke Kenneth Casso... add comment string
2018-10-30 Luke Kenneth Casso... add extra unit tests
2018-10-30 Luke Kenneth Casso... add VL arg to macro
2018-10-30 Luke Kenneth Casso... add isvec args to test elwidth macros
2018-10-29 Luke Kenneth Casso... add sv store elementwidth test
2018-10-29 Luke Kenneth Casso... add extra ld elwidth tests, add #defines for elwidths
2018-10-29 Luke Kenneth Casso... add extra tests, change data (unsigned in places)
2018-10-29 Luke Kenneth Casso... add sv_ld_elwidth test
2018-10-29 Luke Kenneth Casso... add in TODO list
2018-10-26 Luke Kenneth Casso... extend addw bitwidth test to 3 registers
2018-10-26 Luke Kenneth Casso... put in stuff that should not be overwritten
2018-10-26 Luke Kenneth Casso... correct addw elwidth test
2018-10-26 Luke Kenneth Casso... sv addw variable elwidth unit test
2018-10-26 Luke Kenneth Casso... sort out registers and add extra unit tests for add...
2018-10-26 Luke Kenneth Casso... add sv_add_elwidth unit test
2018-10-16 Luke Kenneth Casso... modified VL and MVL CSRs to range from 1-XLEN rather...
2018-10-09 Luke Kenneth Casso... add sv vectorised predicated beq test
2018-10-09 Luke Kenneth Casso... alter unit tests to match change in CSR table format
2018-10-07 Luke Kenneth Casso... add cleanup and comments to sv lwsp pred test
2018-10-07 Luke Kenneth Casso... add predicated version of c.lwsp sv unit test
2018-10-07 Luke Kenneth Casso... add 3rd register to c.swsp
2018-10-07 Luke Kenneth Casso... add 3 registers to sv c.lwsp
2018-10-07 Luke Kenneth Casso... add s.swsp sv test
2018-10-06 Luke Kenneth Casso... add sv c_lwsp unit test
2018-10-05 Luke Kenneth Casso... whoops overwrote x2
2018-10-04 Luke Kenneth Casso... add twin-predicated sv c_mv unit test (no zeroing)
2018-10-04 Luke Kenneth Casso... add sv c.mv twin-predication unit test
2018-10-02 Luke Kenneth Casso... actually sv vector-vector add worked fine
2018-10-02 Luke Kenneth Casso... add rv64ud sv fadd test, shows flaw in loop for 3-arg...
2018-10-01 Luke Kenneth Casso... add vector-vector sv add
2018-10-01 Luke Kenneth Casso... add sv addi predicated unit test, including inversion...
2018-10-01 Luke Kenneth Casso... add extra sv test comments
2018-10-01 Luke Kenneth Casso... update sv test comments
2018-10-01 Luke Kenneth Casso... add sv scalar src test which highlighted flaw in spike-sv
2018-10-01 Luke Kenneth Casso... add redirection sv unit test
2018-10-01 Luke Kenneth Casso... augment sv_addi test using macros
2018-10-01 Luke Kenneth Casso... add first unit test for simple-v
2018-09-08 Andrew WatermanMerge branch 'tommythorn-master'
2018-09-08 Tommy ThornRV64 s{ll,ra,rl}w tests with non-canonical values
2018-09-07 Andrew WatermanRevert "breakpoint.S: Don't assume trigger is hardwired...
2018-09-06 Tommy Thornbreakpoint.S: Don't assume trigger is hardwired to...
2018-08-22 Tim NewsomeMerge branch 'master' of https://github.com/riscv/riscv...
2018-08-21 Srivatsa YogendraChanging the register mstatus is read into (#152)
2018-08-21 Andrew WatermanRevert "Fix to solve the failing tests shamt, csr and...
2018-08-18 Srivatsa YogendraFix to solve the failing tests shamt, csr and scall...
2018-08-17 Srivatsa Yogendramaking mtvec_handler global (#150)
2018-07-09 Andrew WatermanCheck that SC yields the load reservation
2018-05-01 Christopher Celio[rv64ua/lrsc] Initialize memory read out. (#135)
2018-04-09 Andrei TatarnikovFix #120: Instructions 'sll' are replaced with 'slli...
2018-03-21 Andrew WatermanMake misa.C test conform to Hauser proposal
2018-02-27 Andrew WatermanAdd test for clearing misa.C while PC is misaligned...
2018-01-03 Andrew WatermanTest access exception behavior for illegal addresses...
2017-11-27 Andrew WatermanRename sbadaddr to satp
2017-11-27 TorbjørnRv32ud tests (#108)
2017-11-22 Christopher CelioCheck sepc for rv64si/scall test. (#107)
2017-11-20 Andrew WatermanCheck mtval in rv64mi-p-illegal (#104)
2017-11-12 Andrew WatermanMake sure that code is 4-byte aligned before disabling...
2017-11-10 Andrew WatermanMake rv64mi-p-ecall work when U-mode is not present
2017-11-10 Andrew WatermanUse mstatus.MPP to check existence of U-mode
2017-11-01 Christopher CelioSBREAK test now checks EPC value. (#92)
2017-10-30 Richard XiaRemove cache miss test from last AMO test. (#88)
2017-10-30 Richard XiaDeclare trap handlers as global symbols. (#87)
2017-10-27 Andrew WatermanVerify that mtval/stval is written correctly on misalig...
2017-10-27 Richard XiaFix rv64mi-csr for the case where U-mode is not availab...
2017-09-12 Tim NewsomeMerge pull request #69 from riscv/multicore
2017-09-01 Andrew WatermanImprove ma_fetch test to cover JAL and branches
2017-08-08 Palmer DabbeltMerge pull request #62 from richardxia/only-emit-f...
2017-08-07 Richard Xiarv64[ms]i-csr: Only emit F instructions when compiled...
2017-08-04 Andrew WatermanRV32 div tests should use -2^31 for min value, not...
2017-08-04 Andrew WatermanImprove RVC test
2017-05-25 Palmer DabbeltMerge pull request #53 from richardxia/fail-if-simulato...
2017-05-22 Andrew WatermanminNum -> minimumNumber
2017-05-18 Megan WachsMerge pull request #52 from riscv/vcs_sim_cmd
2017-05-17 Andrew WatermanManually assemble bad shift amount, since assembler...
2017-05-16 Palmer DabbeltMerge pull request #47 from riscv/debug-0.13
2017-05-05 Andrew WatermanCheck UXL in sstatus
2017-05-05 Andrew WatermanTest that superpage PTEs trap when PPN LSBs are set
2017-05-05 Andrew WatermanRegularize control flow in dirty-bit test
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/newprogram' into...
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-15 Andrew WatermanFix illegal-instruction test when S-mode is not implemented
2017-04-11 Andrew WatermanImprove fp ldst/move tests; remove redundant fsgnj...
2017-04-08 Andrew WatermanRetrofit rv64mi-p-illegal to test vectored interrupts
2017-04-07 Andrew WatermanRemove defunct IPI tests
2017-04-06 Andrew WatermanMake ma_addr test work for systems with misaligned...
2017-03-30 Andrew WatermanExpand dirty-bit test to test MPRV and SUM
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2017-03-22 Andrew WatermanClean up benchmarks build
2017-03-21 Andrew WatermanAllow supervisor access to user pages in dirty-bit...
2017-03-21 Andrew WatermanAvoid x3 (gp), which is now TESTNUM
2017-03-13 Andrew WatermanTest mstatus.TW, mstatus.TVM, and mstatus.TSR features
2017-03-09 Andrew WatermanDon't link ISA tests against libc
2017-03-09 Andrew WatermanPermit flexible dirty-bit behavior
2017-03-09 Andrew WatermanCheck mbadaddr in ma_addr test
2017-02-02 Andrew WatermanUse NaN macros
2017-02-02 Andrew WatermanTest FMIN/FMAX NaN behavior
2017-02-01 Andrew WatermanTest qNaN and sNaN inputs to FP comparisons
2017-01-04 Andrew WatermanSpecify Spike ISA explicitly
next