1 """Simple GPIO peripheral on wishbone
3 This is an extremely simple GPIO peripheral intended for use in XICS
4 testing, however it could also be used as an actual GPIO peripheral
7 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Array
8 from nmigen
.utils
import log2_int
9 from nmigen
.cli
import rtlil
10 from soc
.minerva
.wishbone
import make_wb_layout
11 from nmutil
.util
import wrap
12 from soc
.bus
.test
.wb_rw
import wb_read
, wb_write
16 from nmigen
.sim
.cxxsim
import Simulator
, Settle
18 from nmigen
.back
.pysim
import Simulator
, Settle
21 class SimpleGPIO(Elaboratable
):
23 def __init__(self
, n_gpio
=16):
30 self
.bus
= Record(make_wb_layout(spec
), name
="gpio_wb")
31 self
.gpio_o
= Signal(n_gpio
)
33 def elaborate(self
, platform
):
35 comb
, sync
= m
.d
.comb
, m
.d
.sync
38 wb_rd_data
= bus
.dat_r
39 wb_wr_data
= bus
.dat_w
45 gpio_addr
= Signal(log2_int(self
.n_gpio
))
46 gpio_a
= Array(list(gpio_o
))
48 with m
.If(bus
.cyc
& bus
.stb
):
49 comb
+= wb_ack
.eq(1) # always ack
50 comb
+= gpio_addr
.eq(bus
.adr
)
51 with m
.If(bus
.we
): # write
52 sync
+= gpio_a
[gpio_addr
].eq(wb_wr_data
[0])
54 comb
+= wb_rd_data
.eq(gpio_a
[gpio_addr
])
59 for field
in self
.bus
.fields
.values():
68 def read_gpio(gpio
, addr
):
69 data
= yield from wb_read(gpio
.bus
, addr
)
70 print ("gpio%d" % addr
, hex(data
), bin(data
))
77 data
= yield from read_gpio(gpio
, 0) # read gpio addr 0
80 yield from wb_write(gpio
.bus
, 0, 1) # write gpio addr 0
82 data
= yield from read_gpio(gpio
, 0) # read gpio addr 0
86 data
= yield from read_gpio(gpio
, 1) # read gpio addr 1
89 yield from wb_write(gpio
.bus
, 1, 1) # write gpio addr 1
91 data
= yield from read_gpio(gpio
, 1) # read gpio addr 1
95 data
= yield from read_gpio(gpio
, 0) # read gpio addr 0
98 yield from wb_write(gpio
.bus
, 0, 0) # write gpio addr 0
100 data
= yield from read_gpio(gpio
, 0) # read gpio addr 0
107 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
108 with
open("test_gpio.il", "w") as f
:
112 m
.submodules
.xics_icp
= dut
117 sim
.add_sync_process(wrap(sim_gpio(dut
)))
118 sim_writer
= sim
.write_vcd('test_gpio.vcd')
123 if __name__
== '__main__':