Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / config / ifetch.py
1 """ConfigureableFetchUnit and ConfigMemoryPortInterface
2
3 allows the type of FetchUnit to be run-time selectable
4
5 this allows the same code to be used for both small unit tests
6 as well as larger ones and so on, without needing large amounts
7 of unnecessarily-duplicated code
8 """
9 from soc.experiment.imem import TestMemFetchUnit
10 from soc.bus.test.test_minerva import TestSRAMBareFetchUnit
11 from soc.minerva.units.fetch import BareFetchUnit
12
13
14 class ConfigFetchUnit:
15 def __init__(self, pspec):
16 fudict = {'testmem': TestMemFetchUnit,
17 'test_bare_wb': TestSRAMBareFetchUnit,
18 'bare_wb': BareFetchUnit,
19 #'test_cache_wb': TestCacheFetchUnit
20 }
21 self.pspec = pspec
22 if self.pspec.imem_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
23 # XXX BLECH! use pspec to transfer the I-Cache which is
24 # created down inside LoadStore1!
25 self.fu = icache = pspec.icache # ICache already FetchUnitInterface
26 # tell I-Cache to connect up to its FetchUnitInterface
27 icache.use_fetch_interface()
28 return
29
30 fukls = fudict[pspec.imem_ifacetype]
31 self.fu = fukls(pspec)
32
33 def wb_bus(self):
34 return self.fu.ibus
35